NJW1504/1508
PLL Synthesizer with I C Bus for TV Tuner
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DESCRIPTION
The NJW1504/1508 are a PLL frequency synthesizer especially
designed for TV and VCR tuning systems and consists of PLL circuit
and a prescaler which operates up to 1.0GHz, built into one chip.
The NJW1504/1508 are controlled through an I
2
C-bus.
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FEATURES
•
Operating Voltage 5V
•
Low Operating Current : 15mA typ. @Vcc=5V
•
Prescaler accepts frequencies up to 1GHz on chip
•
Reference Signal :
NJW1504: Reference Signal Oscillator with peripheral of Xtal on chip
NJW1508: Buffer Amplifier for External Reference Signal on chip
•
34V max. tuning voltage output
•
Package Outline: SSOP16
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PACKAGE OUTLINE
2
NJW1504V/NJW1508V
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BLOCK DIAGRAM
BS0-BS3
VCC3
VCC1
5V GND
BAND SW
4bit
4bit
Latch
I2C
Receive
Bus
r
15bit
Latch
ADRS
SDA
SCL
HF IN
PreAMP
CP
VCC2
1/8
Programmable
Divider 15bit
8bit
Latch
OSCOUT
Phase
OUT
AMP
Phase
Comp.
1/1024
1/512
(1/640)
Ref.
Divider
X’tal
OSC
XTAL
AMPOUT
(Note)
Purchase of I
2
C components of New Japan RadioCo.,Ltd or one of its sublicensed Associated Companies conveys a license
under the Philips I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C
standard specification as definedby by Philips.
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NJW1504/1508
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ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply Voltage (Vcc1, 3)
Vcc1, Vcc3
Supply Voltage (Vcc2)
Vcc2
2
Input Voltage (except I C bus)
Vi
Output Voltage (except I
2
C bus)
Vo
I
2
C bus Input Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range
V
iiic
P
D
T
opr
T
stg
(T
A
=25°C)
Unit
V
V
V
V
V
mW
°C
°C
(T
A
=25°C)
Unit
V
V
MHz
MHz
KHz
uS
uS
uS
uS
uS
uS
nS
nS
nS
uS
Ratings
-0.3 to +6.5
-0.3 to +36
-0.3 to Vcc+0.3
-0.3 to Vcc+0.3
-0.3 to 6.5
300
-20 to +85
-40 to +125
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RECOMMENDED OPERATING CONDITION
Parameter
Condition
Symbol
Operating Voltage
Vcc1, Vcc3
Vcc1, Vcc3
Operating Voltage
Vcc2
Vcc2
X’tal Operating Range
f
xtal
HF Input Frequency
Input= -20dBm
f
hf
Clock Frequency
f
SCL
Bus Free Time
t
BUF
Data Hold Time
t
HDSTA
SCL Low Hold Time
t
LOW
SCL High Hold Time
t
HIGH
2
Set-up Time
Refer to I C bus Timing Chart
t
SUSTA
Data Hold Time
t
HDDAT
Data Set-up Time
t
SUDAT
Rise Time
t
R
Fall Time
t
F
Data Set-up Time
t
SUSTO
Min.
4.5
0
3.15
80
0
4.7
2
4.7
2
2
0
250
-
-
4
Typ.
5
-
4
-
-
-
-
-
-
-
-
-
-
-
-
Max.
5.5
34
4.05
1000
100
-
-
-
-
-
-
-
1000
300
-
SDA
t BUF
t LOW
t HIG H
t SU;DAT
t
HD;STA
SCL
t
HD;STA
t
t HD;DAT
t
R
F
t
SU;STA
t S U;STO
I C bus Timing Chart
V
IH
min(0.7 Vcc1) and V
IL
max(0.3 Vcc1)
2
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NJW1504/1508
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ELECTRICAL CHARACTERISTICS
Parameter
Condition
Operating Current 1
f
HF
=100MHz
Operating Current 2
AMPOUT: Low Level
AMP Input Current
Phase OUT: High Imp (2.5V)
ANP OUT: Low Level
AMP Output Current
AMPOUT Input=5V
AMP Gain
f=1KHz
Phase Comparator
Current Source
Output Current
Phase Comparator
Current Sink
Output Current
Band Switch
“L” Output Current
BS0=BS1=0.3V
“H” Output Current
BS0=BS1=4.7V
“L” Output Current
BS2=BS3=0.3V
“H” Output Current
BS2=BS3=4.7V
2
I C bus
“H” Input Current
SCL, SDA Terminal
“L” Input Current
SCL, SDA Terminal
“H” Input Voltage Range
SCL, SDA Terminal
“L” Input Voltage Range
SCL, SDA Terminal
ACK Sink Current
ACK Output, SDA=0.4V
(Vcc1,3=5V,Vcc2=34V,T
A
=25°C)
Symbol Min.
Typ.
Max.
Unit
I
CC
12
15
21
mA
I
CC
2
-
1.6
-
mA
I
IN
(-50)
0.1
(50)
nA
I
OUT
AV
I
sourse
I
sink
I
OBS0-1L
I
OBS0-1H
I
OBS2-3L
I
OBS2-3H
I
IN
H
I
IN
L
V
IH
V
IL
V
ACK
-
40
190
-400
-2.0
11.0
-2.0
5.5
-5
-5
3.5
0
3
-
50
280
-280
-1
15.0
-1.0
7.5
0
0
-
-
-
-2
60
400
-190
0
-
0
-
5
5
5.3
1.5
-
mA
dB
uA
uA
mA
mA
mA
mA
uA
uA
V
V
mA
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NJW1504/1508
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TEST CIRCUIT
VS3
5V
2mV
1kHz
5V
VS2
2.5V
34V
SDA
SCL
OSC OUT
18p
100
4MHz
270
316k
16
15
14
13
12
11
10
9
OSC OUT
AMP OUT
ADRS
VCC2
XTAL
SDA
SCL
VCC1
GND
VCC3
BS3
BS2
1
1n
2
3
4
5
6
BS1
HF
7
50
SG
-20dBm
5V
BS0
8
CP
VS1
4.7V or 0.3V
COUNTER
-4-
NJW1504/1508
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I
2
C bus Protocols
2
The input information, which consists of chip address and next two or four byte data, is received by I C bus
receiver. The allowable I
2
C bus protocols are as follows.
(1) STA CA CB BB STO
(2) STA CA D1 D2 STO
(3) STA CA CB BB D1 D2 STO
(4) STA CA D1 D2 CB BB STO
STA: Start Condition
STO: Stop Condition
CA: Chip Address
CB: Control Byte
BB: Band switch Byte
D1: Divider Byte 1
D2: Divider Byte 2
For suitable circuit operation,5-byte data should have chip address, 2-byte control data, band data, and 2-byte
divider byte. Following chip address. 2-byte data is received. For distinction of each data, first and third data
byte has a function bit. As function bit, divider byte has “1” and control/band data has “0”.
SDA
SCL
STA
1-7
ADDRESS
8
R/W
9
ACK
1 -7
DATA
8
9
ACK
9
ACK
STO
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