÷1/÷2 Differential-to-LVCMOS/LVTTL
Clock Generator
Data Sheet
87021I
G
ENERAL
D
ESCRIPTION
The 87021I is a high performance ÷1/÷2 Differential-to-LVCMOS/
LVTTL Clock Generator and a member of the family of High
Performance Clock Solutions from IDT. The CLK, nCLK pair can
accept most standard differential input levels. Guaranteed part-
to-part skew characteristics make the 87021I ideal for those clock
distribution applications demanding well defined performance
and repeatability.
F
EATURES
• Two single-ended LVCMOS/LVTTL outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 250MHz
• Additive phase jitter, RMS: 0.18ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 450ps (maximum)
• Propagation delay: 3.4ns (maximum)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Availalbe in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
÷1
CLK
nCLK
P
IN
A
SSIGNMENT
0
Q0
CLK
nCLK
MR
F_SEL
1
2
3
4
8
7
6
5
V
DD
Q0
Q1
GND
R ÷2
MR
1
Q1
87021I
8-Lead SOIC
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
F_SEL
©2016 Integrated Device Technology, Inc
1
Revision B January 25, 2016
87021I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
Name
CLK
nCLK
MR
Input
Input
Input
Type
Pullup
Description
Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal divid-
Pulldown
ers and the outputs are enabled. LVCMOS / LVTTL interface levels. See
Table 3.
Selects divider value for Qx outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Power supply ground.
Singled-ended output. LVCMOS/LVTTL interface levels.
Singled-ended output. LVCMOS/LVTTL interface levels.
Positive supply pin.
4
5
6
7
8
F_SEL
GND
Q1
Q0
V
DD
Input
Power
Output
Output
Power
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.465V
V
DD
= 3.465V
V
DD
= 2.625V
Test Conditions
Minimum
Typical
4
24
16
51
51
9
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
©2016 Integrated Device Technology, Inc
2
Revision B January 25, 2016
87021I Data Sheet
T
ABLE
3. F
UNCTION
T
ABLE
MR
1
0
0
F_SEL
X
0
1
Divide Value
Reset: Q0, Q1 outputs low
÷1
÷2
CLOCK
MR
÷1
CLOCK
MR
÷2
F
IGURE
1. T
IMING
D
IAGRAM
©2016 Integrated Device Technology, Inc
3
Revision B January 25, 2016
87021I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
103°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
60
Units
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
35
Units
V
mA
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V
V
DD
= 3.465V or 2.625V
-5
2.6
0.5
Test Conditions
Minimum
1.3
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
DD
/2. See Parameter Measurement Information section,
“3.3V Output Load Test Circuit” diagram.
T
ABLE
4D. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V
V
DD
= 2.625V
-5
1.8
0.5
Test Conditions
Minimum
1.1
-0.3
Typical
Maximum
V
DD
+ 0.3
0.5
150
Units
V
V
µA
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
DD
/2. See Parameter Measurement Information section,
“2.5V Output Load Test Circuit” diagram.
©2016 Integrated Device Technology, Inc
4
Revision B January 25, 2016
87021I Data Sheet
T
ABLE
4E. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
OR
V
DD
= 2.5V±5%, T
A
= -40°C
TO
85°C
Minimum
Typical
Maximum
150
5
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Units
µA
µA
µA
µA
V
V
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1
NOTE 1: Common mode voltage is defined as V
IH
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tjit
tsk(pp)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay;
CLK to Qx
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Sec-
tion
Part-to-Part Skew; NOTE 2, 3
Output Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle;
NOTE 5
20% to 80%
Fout
≤
133MHz
Fout > 133MHz
250
45
40
2.1
250MHz, Integration Range:
12kHz – 20MHz
0.18
450
50
700
55
60
Test Conditions
Minimum
Typical
Maximum
250
3.4
Units
MHz
ns
ps
ps
ps
ps
%
%
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 5: Output Duty Cycle assuming 50% input duty cycle.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tjit
tsk(pp)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay;
CLK to Qx
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Sec-
tion
Part-to-Part Skew; NOTE 2, 3
Output Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle;
NOTE 5
20% to 80%
Fout
≤
133MHz
Fout > 133MHz
250
45
40
2.7
250MHz, Integration Range:
12kHz – 20MHz
0.3
450
25
700
55
60
Test Conditions
Minimum
Typical
Maximum
250
3.4
Units
MHz
ns
ps
ps
ps
ps
%
%
For NOTES, please see above Table 5A.
©2016 Integrated Device Technology, Inc
5
Revision B January 25, 2016
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