MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8−bit static shift registers are
constructed with MOS P−channel and N−channel enhancement mode
devices in a single monolithic structure. These shift registers find primary
use in parallel−to−serial data conversion, synchronous and asynchronous
parallel input, serial output data queueing; and other general purpose
register applications requiring low power and/or high noise immunity.
Features
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Synchronous Parallel Input/Serial Output (MC14014B)
Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
“Q” Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
MC14014B Pin−for−Pin Replacement for CD4014B
MC14021B Pin−for−Pin Replacement for CD4021B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
P8
Q6
Q8
P4
P3
P2
P
1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
P7
P6
P5
Q7
D
S
C
P/S
V
SS
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
MARKING DIAGRAM
16
140xxBG
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 9
Publication Order Number:
MC14014B/D
MC14014B, MC14021B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
V
IH
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
−55_C
25_C
125_C
Characteristic
Symbol
V
OL
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–2.4
–0.51
−1.3
−3.4
0.51
1.3
3.4
−
−
−
−
−
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
–4.2
–0.88
–2.25
−8.8
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–1.7
−0.36
–0.9
−2.4
0.36
0.9
2.4
−
−
−
−
−
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
“0” Level
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
15
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
15
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
Vdc
“1” Level
V
OH
Vdc
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
“0” Level
V
IL
Vdc
I
OH
Source
mAdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (0.75
mA/kHz)
f + I
DD
I
T
= (1.50
mA/kHz)
f + I
DD
I
T
= (2.25
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
− 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
− V
SS
) in volts, f in kHz is input frequency, and k = 0.0015.
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MC14014B, MC14021B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
t
TLH
,
t
THL
V
DD
Vdc
5.0
10
15
Min
−
−
−
Typ
(Note 6)
100
50
40
Max
200
100
80
ns
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
−
−
−
400
175
135
−
−
−
400
175
135
200
100
80
20
20
25
350
80
60
45
35
35
50
45
45
−
−
−
400
170
115
150
75
40
3.0
6.0
8.0
150
75
40
100
50
40
– 2.5
– 10
0
150
50
30
0
0
5
25
20
20
−
−
−
800
340
230
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
15
5
4
ns
Unit
ns
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Propagation Delay Time (Clock to Q, P/S to Q)
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 315 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 137 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 90 ns
Clock Pulse Width
t
PLH
,
t
PHL
t
WH
Clock Frequency
f
cl
MHz
Parallel/Serial Control Pulse Width
t
WH
ns
Setup Time
P/S to Clock
Hold Time
Clock to P/S
Setup Time
Data (Parallel or Serial) to
Clock or P/S
Hold Time
Clock to D
s
Hold Time
Clock to P
n
Input Clock Rise Time
t
su
ns
t
h
ns
t
su
ns
t
h
ns
t
h
ns
t
r(cl)
ms
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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