Changes to Table 3, Endnote 1, and Figure 2................................ 5
5/11—Rev. 0 to Rev. A
Changes to Table 6, LRSEL Pin Description................................. 7
10/10—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
SPECIFICATIONS
SSM2517
PVDD = 5.0 V, VDD = 1.8 V, f
S
= 128×, T
A
= 25°C, R
L
= 8 Ω + 33 μH, unless otherwise noted. When f
S
= 128×, PDM clock = 6.144 MHz;
when f
S
= 64×, PDM clock = 3.072 MHz.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power
Symbol
P
O
Test Conditions/Comments
f = 1 kHz, BW = 20 kHz
R
L
= 4 Ω, THD = 1%, PVDD = 5.0 V
R
L
= 8 Ω, THD = 1%, PVDD = 5.0 V
R
L
= 4 Ω, THD = 1%, PVDD = 3.6 V
R
L
= 8 Ω, THD = 1%, PVDD = 3.6 V
R
L
= 4 Ω, THD = 10%, PVDD = 3.6 V
R
L
= 8 Ω, THD = 10%, PVDD = 3.6 V
f = 1 kHz, BW = 20 kHz
P
O
= 100 mW into 8 Ω, PVDD = 3.6 V
P
O
= 500 mW into 8 Ω, PVDD = 3.6 V
P
O
= 1 W into 8 Ω, PVDD = 5.0 V
R
L
= 4 Ω, −6 dBFS input, PVDD = 5.0 V
R
L
= 8 Ω, −6 dBFS input, PVDD = 5.0 V
R
L
= 4 Ω, −6 dBFS input, PVDD = 3.6 V
R
L
= 8 Ω, −6 dBFS input, PVDD = 3.6 V
P
O
= 2.4 W into 4 Ω, PVDD = 5.0 V
P
O
= 1.38 W into 8 Ω, PVDD = 5.0 V
No input
−6 dBFS PDM input, BTL output,
f = 1 kHz
PVDD = 3.6 V
PVDD = 5.0 V
Gain = 6 dB
f
S
= 64×
f
S
= 128×
1.84
3.68
Min
Typ
Max
Unit
2.4
1.38
1.2
0.7
1.5
0.9
0.035
0.1
0.12
3.6
1.0
5.2
2.3
86
92
290
W
W
W
W
W
W
%
%
%
%
%
%
%
%
%
kHz
Total Harmonic Distortion Plus Noise
THD + N
Efficiency
Average Switching Frequency
Closed-Loop Gain
η
f
SW
Gain
Differential Output Offset Voltage
Low Power Mode Wake Time
Input Sampling Frequency
POWER SUPPLY
Supply Voltage Range
Amplifier Power Supply
Digital Power Supply
Power Supply Rejection Ratio
Supply Current, H-Bridge
V
OOS
t
WAKE
f
S
3.5
4.78
0.5
3.072
6.144
0.5
3.23
6.46
V
P
V
P
mV
ms
MHz
MHz
PVDD
VDD
PSRR
GSM
I
PVDD
2.5
1.62
V
RIPPLE
= 100 mV at 217 Hz
Dither input, 8 Ω + 33 μH load
PVDD = 5.0 V, f
S
= 64×
PVDD = 5.0 V, f
S
= 128×
PVDD = 3.6 V, f
S
= 64×
PVDD = 3.6 V, f
S
= 128×
PVDD = 2.5 V, f
S
= 64×
PVDD = 2.5 V, f
S
= 128×
PVDD = 5.0 V
Dither input, 8 Ω + 33 μH load
VDD = 3.3 V, f
S
= 64×
VDD = 3.3 V, f
S
= 128×
VDD = 1.8 V, f
S
= 64×
VDD = 1.8 V, f
S
= 128×
3.6
1.8
85
3.1
3.2
2.6
2.7
2.2
2.3
0.0
100
1.3
2.4
0.6
1.2
5.5
3.6
V
V
dB
mA
mA
mA
mA
mA
mA
mA
nA
mA
mA
mA
mA
Standby Current
Power-Down Current
Supply Current, Modulator
I
VDD
Rev. B | Page 3 of 16
SSM2517
Parameter
Standby Current
Shutdown Current
NOISE PERFORMANCE
Output Voltage Noise
Symbol
Test Conditions/Comments
VDD = 1.8 V, f
S
= 64×
VDD = 1.8 V, f
S
= 128×
VDD = 3.3 V
VDD = 1.8 V
Dithered input, A-weighted
PVDD = 3.6 V, f
S
= 64×
PVDD = 3.6 V, f
S
= 128×
PVDD = 5.0 V, f
S
= 64×
PVDD = 5.0 V, f
S
= 128×
P
O
= 1.38 W, PVDD = 5.0 V, R
L
= 8 Ω,
A-weighted
f
S
= 64×
f
S
= 128×
Min
Typ
57
114
3.0
0.9
Data Sheet
Max
Unit
μA
μA
μA
μA
e
n
43
52
52
60
μV
μV
μV
μV
Signal-to-Noise Ratio
SNR
96
95
dB
dB
DIGITAL INPUT SPECIFICATIONS
Table 2.
Parameter
INPUT SPECIFICATIONS
Input Voltage High
PCLK, PDAT, LRSEL Pins
GAIN_FS Pin
Input Voltage Low
PCLK, PDAT, LRSEL Pins
GAIN_FS Pin
Input Leakage High
PDAT, LRSEL, GAIN_FS Pins
PCLK Pin
Input Leakage Low
PDAT, LRSEL, GAIN_FS Pins
PCLK Pin
Input Capacitance
Symbol
V
IH
0.7 × VDD
1.35
V
IL
−0.3
−0.3
I
IH
1
3
I
IL
1
3
5
μA
μA
pF
μA
μA
0.3 × VDD
+0.35
3.6
5.5
V
V
V
V
V
Min
Typ
Max
Unit
Rev. B | Page 4 of 16
Data Sheet
PDM INTERFACE DIGITAL TIMING SPECIFICATIONS
Table 3.
Parameter
t
DS
t
DE
1
SSM2517
t
MIN
44
Limit
t
MAX
7
Unit
ns
ns
Description
Valid data start time
1
Valid data end time
1
The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge. It is not necessary to delay the data line transition until after the
clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated
in Figure 2; it may transition at any other time. Timing is measured from 70% of VDD on the rising edge or 30% VDD on the falling edge.
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