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GS8330DW72C-250

产品描述Double Late Write SigmaRAM
产品类别存储    存储   
文件大小580KB,共30页
制造商GSI Technology
官网地址http://www.gsitechnology.com/
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GS8330DW72C-250概述

Double Late Write SigmaRAM

GS8330DW72C-250规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称GSI Technology
零件包装代码BGA
包装说明BGA,
针数209
Reach Compliance Codecompli
ECCN代码3A991.B.2.B
最长访问时间2.1 ns
其他特性PIPELINED ARCHITECTURE
JESD-30 代码R-PBGA-B209
长度22 mm
内存密度37748736 bi
内存集成电路类型STANDARD SRAM
内存宽度72
湿度敏感等级3
功能数量1
端子数量209
字数524288 words
字数代码512000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织512KX72
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装形状RECTANGULAR
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
认证状态Not Qualified
最大供电电压 (Vsup)1.95 V
最小供电电压 (Vsup)1.7 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子形式BALL
端子节距1 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度14 mm

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Preliminary
GS8330DW36/72C-250/200
209-Bump BGA
Commercial Temp
Industrial Temp
36Mb
Σ
1x1Dp CMOS I/O
Double Late Write SigmaRAM™
200 MHz–250 MHz
1.8 V V
DD
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAM
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 72Mb and 144Mb devices
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
-250
4.0 ns
2.1 ns
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
Σ
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
SigmaRAM Family Overview
GS8330DW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 37,748,736-bit (36Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Σ
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
ΣRAM
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Σ
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Rev: 1.00 6/2003
1/30
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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