IS61VPD51236a IS61VPD102418a
IS61lPD51236a IS61lPD102418a
512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPElINED,
DOUBlE CYClE DESElECT STaTIC RaM
JUlY 2008
FEaTURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPD: V
dd
3.3V + 5%,
V
ddq
3.3V/2.5V + 5%
VPD: V
dd
2.5V + 5%,
V
ddq
2.5V + 5%
• JEDEC 100-Pin TQFP and 165-pin PBGA
package
• Lead-free available
DESCRIPTION
The
ISSI
IS61LPD/VPD51236A and IS61LPD/VP-
D102418A are high-speed, low-power synchronous
static RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61LPD/VPD51236A is organized as 524,288 words
by 36 bits, and the IS61LPD/VPD102418A is organized
as 1,048,576 words by 18 bits. Fabricated with
ISSI
's
advanced CMOS technology, the device integrates a
2-bit burst counter, high-speed SRAM core, and high-
drive capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FaST aCCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
1
综合技术交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
