DATASHEET
ISL6140, ISL6150
Negative Voltage Hot Plug Controller
The ISL6140 is an 8 Ld, negative voltage hot plug
controller that allows a board to be safely inserted and
removed from a live backplane. Inrush current is
limited to a programmable value by controlling the
gate voltage of an external N-channel pass transistor.
The pass transistor is turned off if the input voltage is
less than the undervoltage threshold, or greater than
the overvoltage threshold. A programmable electronic
circuit breaker protects the system against shorts. The
active low PWRGD signal can be used to directly enable
a power module (with a low enable input)
The ISL6150 is the same part, but with an active high
PWRGD signal.
FN9039
Rev 5.00
December 3, 2015
Features
• Low Side External NFET Switch
• Operates from -10V to -80V (-100V absolute max
rating) or +10V to +80V (+100V absolute max
rating)
• Programmable Inrush Current
• Programmable Electronic Circuit Breaker
(overcurrent shutdown)
• Programmable Overvoltage Protection
• Programmable Undervoltage Lockout
• Power Good Control Output
- PWRGD Active High: (H Version) ISL6150
- PWRGD active Low: (L Version) ISL6140
• Pb-free available (RoHS compliant)
Applications
• VoIP (Voice over Internet Protocol) Servers
• Telecom systems at -48V
• Negative Power Supply Control
• +24V Wireless Base Station Power
Related Literature
• ISL6140/50EVAL1 Board Set, AN9967
• ISL6116 Hot Plug Controller, FN9100
NOTE: See www.intersil.com/hotplug for more information.
Typical Application
GND
R
4
UV
R
5
OV
R
6
NOTE: (RL and CL are the Load)
V
EE
SENSE
GATE
C
1
R
3
DRAIN
C
2
R
L
-48V IN
R
1
Q
1
-48V
OUT
(LOAD)
C
L
GND
V
DD
ISL6140
PWRGD
R
2
R
5
= 9.09k (1%)
R
6
= 10k (1%)
C
1
= 150nF (25V)
R
2
= 10 (5%)
R
3
= 18k (5%)
R
4
= 562k (1%)
C
2
= 3.3nF (100V)
Q
1
= IRF530 (100V, 17A, 0.11)
R
1
= 0.02 (1%)
C
L
= 100µF (100V)
FN9039 Rev 5.00
December 3, 2015
Page 1 of 20
ISL6140, ISL6150
Pin Configuration
ISL6140, ISL6150
(8 LD SOIC)
TOP VIEW
PWRGD/PWRGD 1
OV
UV
V
EE
2
3
4
8 V
DD
7 DRAIN
6 GATE
5 SENSE
ISL6140 has active Low (L version) PWRGD output pin
ISL6150 has active High (H version) PWRGD output pin
Ordering Information
PART
NUMBER
(Notes 2, 3)
ISL6140CBZ
ISL6140CBZ-T (Note 1)
ISL6140IBZ-T (Note 1)
ISL6140IBZ
PART MARKING
ISL61 40CBZ
ISL61 40CBZ
ISL61 40IBZ
ISL61 40IBZ
TEMP.
RANGE (°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
PACKAGE
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
PKG.
DWG. #
M8.15
M8.15
M8.15
M8.15
M8.15
ISL 6150CB
ISL6150CB
No longer
available or supported,
recommended replacement:
ISL6150CBZ
ISL6150CBZ
ISL6150CBZ-T (Note 1)
ISL61 50CBZ
ISL61 50CBZ
0 to +70
0 to +70
-40 to +85
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
M8.15
M8.15
M8.15
ISL 6150IB
ISL6150IB-T
No longer
available or supported,
recommended replacement:
ISL6150IBZ-T
ISL6150IBZ
ISL6150IBZ-T (Note 1)
NOTES:
1. Please refer to
TB347
for details on reel specifications.
ISL61 50IBZ
ISL61 50IBZ
-40 to +85
-40 to +85
8 Ld SOIC (Pb-Free)
8 Ld SOIC (Pb-Free)
M8.15
M8.15
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page forISL6140. For more information on MSL please see
techbrief
TB363.
Pin Description
PWRGD (ISL6140; L Version) Pin 1
This digital output is an open-drain pull-down device.
The Power Good comparator looks at the DRAIN pin
voltage compared to the internal VPG reference (VPG is
nominal 1.7V); this essentially measures the voltage
drop across the external FET and sense resistor. If the
voltage drop is small (<1.7V is normal), the PWRGD
pin pulls low (to VEE); this can be used as an active
low enable for an external module. If the voltage drop
is too large (>1.7V indicates some kind of short or
overload condition), the pull-down device shuts off,
and the pin becomes high impedance. Typically, an
external pull-up of some kind is used to pull the pin
high (many brick regulators have a pull-up function
built in).
PWRGD (ISL6150; H Version) Pin 1
This digital output is a variation of an open-drain
pull-down device. The power good comparator is the
same as described above, but the polarity of the output
is reversed, as follows:
FN9039 Rev 5.00
December 3, 2015
Page 2 of 20
ISL6140, ISL6150
If the voltage drop across the FET is too large (>1.7V),
the open drain pull-down device will turn on, and sink
current to the DRAIN pin. If the voltage drop is small
(<1.7V), a 2nd pull-down device in series with a 6.2k
resistor (nominal) sinks current to V
EE
; if the external
pull-up current is low enough (<1mA, for example),
the voltage drop across the resistor will be big enough
to look like a logic high signal (in this example,
1mA*6.2k = 6.2V). This pin can thus be used as an
active high enable signal for an external module.
Note that for both versions, although this is a digital
pin functionally, the logic high level is determined by
the external pull-up device, and the power supply to
which it is connected; the IC will not clamp it below the
V
DD
voltage. Therefore, if the external device does not
have its own clamp, or if it would be damaged by a
high voltage, then an external clamp might be
necessary.
order to turn the GATE back on (assuming the fault
condition has disappeared).
V
EE
Pin 4
This is the most Negative Supply Voltage, such as in a -
48V system. Most of the other signals are referenced
relative to this pin, even though it may be far away
from what is considered a GND reference.
SENSE Pin 5
This analog input measures the voltage drop across an
external sense resistor (between SENSE and VEE), to
determine if the current exceeds an overcurrent trip
point, equal to nominal (50mV/R
SENSE
). Noise spikes
of less than 2µs are filtered out; if longer spikes need
to be filtered, an additional RC time constant can be
added to stretch the time (see Figure 29; note that the
FET must be able to handle the high currents for the
additional time). To disable the overcurrent function,
connect the SENSE pin to V
EE
.
OV (OVERVOLTAGE) Pin 2
This analog input compares the voltage on the pin to
an internal voltage reference (nominal 1.223V). When
the input goes above the reference (low to high
transition), that signifies an OV (overvoltage)
condition, and the GATE pin is immediately pulled low
to shut off the external FET. Since there is 20mV of
nominal hysteresis built in, the GATE will remain off
until the OV pin drops below a 1.203V (nominal) high
to low threshold. A typical application will use an
external resistor divider from V
DD
to V
EE
, to set the OV
level as desired; a three-resistor divider can set both
OV and UV.
GATE Pin 6
This analog output drives the gate of the external FET
used as a pass transistor. The GATE pin is high (FET is
on) when UV pin is high (above its trip point); the OV
pin is low (below its trip point), and there is no
overcurrent condition (V
SENSE
- V
EE
<50mV). If any of
the 3 conditions are violated, the GATE pin will be
pulled low, to shut off the FET.
The Gate is driven high by a weak (-45µA nominal)
pull-up current source, in order to slowly turn on the
FET. It is driven low by a strong (32mA nominal) pull-
down device, in order to shut off the FET very quickly
in the event of an overcurrent or shorted condition.
UV (Undervoltage) Pin 3
This analog input compares the voltage on the pin to
an internal voltage reference (nominal 1.223V). When
the input goes below the reference (high to low
transition), that signifies an UV (Under-Voltage)
condition, and the GATE pin is immediately pulled low
to shut off the external FET. Since there is 20mV of
nominal hysteresis built in, the GATE will remain off
until the UV pin rises above a 1.243V (nominal) low to
high threshold. A typical application will use an
external resistor divider from V
DD
to V
EE
, to set the UV
level as desired; a three-resistor divider can set both
OV and UV.
If there is an overcurrent condition, the GATE pin is
latched off, and the UV pin is then used to reset the
overcurrent latch; the pin must be externally pulled
below its trip point, and brought back up (toggled) in
DRAIN Pin 7
This analog input compares the voltage of the external
FET DRAIN to the internal VPG reference (nominal
1.7V), for the Power Good function.
Note that the Power Good comparator does NOT turn
off the GATE pin. However, whenever the GATE is
turned off (by OV, UV or SENSE), the Power Good
Comparator will usually then switch to the
power-NOT-good state, since an off FET will have the
supply voltage across it.
V
DD
Pin 8
This is the most positive power supply pin. It can range
from +10 to +80V (Relative to V
EE
). If operation down
near 10V is expected, the user should carefully choose
a FET to match up with the reduced GATE voltage
shown in the specification table.
FN9039 Rev 5.00
December 3, 2015
Page 3 of 20
ISL6140, ISL6150
Absolute Maximum Ratings
.
Thermal Information
Thermal Resistance (Typical, Note 4)
JA
(°C/W)
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . .
95
Maximum Junction Temperature (Plastic Package) . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Supply Voltage (V
DD
to V
EE
) . . . . . . . . . . . . . -0.3V to 100V
DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . -0.3V to 100V
UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . -0.3V to 60V
SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . -0.3V to 20V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7 . . .2000V
Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . -40°C to +85°C
Temperature Range (Commercial) . . . . . . . . . 0°C to +70°C
Supply Voltage Range (Typical) . . . . . . . . . . . 36V to +72V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
Electrical Specifications
V
DD
= +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature
range; either Commercial (0°C to +70°C) or Industrial (-40°C to +85°C). Typical specs are
at +25°C.
Boldface limits apply over the operating temperature range, -40°C to
+85°C.
PART NUMBER
OR GRADE
PARAMETER
DC PARAMETRIC
Supply Operating Range
Supply Current
GATE PIN
Gate Pin Pull-Up Current
Gate Pin Pull-Down Current
External Gate Drive
SYMBOL
TEST
CONDITIONS
TEST
MIN
MAX
LEVEL OR
NOTES (Note 7) TYP (Note 7) UNITS
V
DD
I
DD
UV = 3V; OV = V
EE
;
SENSE = V
EE
; V
DD
= 80V
10
0.6
-
0.9
80
1.3
V
mA
I
PU
I
PD
-V
GATE
Gate Drive on, V
GATE =
V
EE
Gate Drive off; any fault
condition
(V
GATE -
V
EE)
, 17V
V
DD
80V
(V
GATE -
V
EE)
, 10V
V
DD
17V
5
-30
24
10
5.4
-45
32
14
6.2
-60
70
15
15
µA
mA
V
V
SENSE PIN
Circuit Breaker Trip Voltage
SENSE Pin Current
UV PIN
UV Pin High Threshold Voltage
UV Pin Low Threshold Voltage
UV Pin Hysteresis
UV Pin Input Current
OV PIN
OV Pin High Threshold Voltage
OV Pin Low Threshold Voltage
OV Pin Hysteresis
OV Pin Input Current
V
OVH
V
OVL
V
OVHY
I
INOV
V
OV
= V
EE
OV Low to High Transition
OV High to Low Transition
1.198
1.165
7
-
1.223
1.203
20
-0.05
1.247
1.232
50
-0.5
V
V
mV
µA
V
UVH
V
UVL
V
UVHY
I
INUV
V
UV
= V
EE
UV Low to High Transition
UV High to Low Transition
1.213
1.198
7
-
1.243
1.223
20
-0.05
1.272
1.247
50
-0.5
V
V
mV
µA
V
CB
I
SENSE
V
CB
= (V
SENSE
- V
EE
)
V
SENSE
= 50mV
40
-
50
0
60
-0.5
mV
µA
FN9039 Rev 5.00
December 3, 2015
Page 4 of 20
ISL6140, ISL6150
Electrical Specifications
V
DD
= +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature
range; either Commercial (0°C to +70°C) or Industrial (-40°C to +85°C). Typical specs are
at +25°C.
Boldface limits apply over the operating temperature range, -40°C to
+85°C. (Continued)
PART NUMBER
OR GRADE
PARAMETER
DRAIN PIN
Power Good Threshold (L to H)
Power Good Threshold (H to L)
Power Good Threshold Hysteresis
Drain Input Bias Current
SYMBOL
TEST
CONDITIONS
TEST
MIN
MAX
LEVEL OR
NOTES (Note 7) TYP (Note 7) UNITS
V
PGLH
V
PGHL
V
PGHY
I
DRAIN
V
DRAIN
- V
EE
, Low to High
Transition
V
DRAIN
- V
EE
, High to Low
Transition
1.55
1.10
0.30
1.70
1.25
0.45
35
1.87
1.42
0.60
60
V
V
V
µA
V
DRAIN
= 48V
10
ISL6140 (PWRGD PIN: L VERSION)
PWRGD Output Low Voltage
V
OL
(V
DRAIN
- V
EE)
< V
PG
I
OUT
= 1mA
I
OUT
= 3mA
I
OUT
= 5mA
Output Leakage
I
OH
V
DRAIN
= 48V, V
PWRGD
= 80V
-
-
-
-
0.28
0.88
1.45
0.05
0.50
1.20
1.95
10
V
µA
V
ISL6150 (PWRGD PIN: H VERSION)
PWRGD Output Low Voltage
(PWRGD-DRAIN)
PWRGD Output Impedance
AC TIMING
OV High to GATE Low
OV Low to GATE High
UV Low to GATE Low
UV High to GATE High
SENSE High to GATE Low
ISL6140 (L VERSION)
DRAIN Low to PWRGD Low
DRAIN High to PWRGD High
ISL6150 (H VERSION)
DRAIN Low to (PWRGD-DRAIN)
High
DRAIN High to (PWRGD-DRAIN)
Low
NOTES:
5. Typical value depends on V
DD
voltage; see Figure 13, “V
GATE
vs V
DD
” (<20V).
6. PWRGD is referenced to DRAIN; V
PWRGD
-V
DRAIN
= 0V.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
t
PHLPG
t
PLHPG
(Figures 1, 4B)
(Figures 1, 4B)
6
6
0.1
0.1
0.9
0.8
2.0
2.0
µs
µs
t
PHLPG
t
PLHPG
(Figures 1, 4A)
(Figures 1, 4A)
0.1
0.1
0.9
0.7
2.0
2.0
µs
µs
t
PHLOV
t
PLHOV
t
PHLUV
t
PLHUV
(Figures 1, 3A)
(Figures 1, 3A)
(Figures 1, 3B)
(Figures 1, 3B)
0.6
1.0
0.6
1.0
2
1.6
7.8
1.3
8.4
3
3.0
12.0
3.0
12.0
4
µs
µs
µs
µs
µs
V
OL
R
OUT
V
DRAIN
= 5V, I
OUT
= 1mA
(V
DRAIN
- V
EE)
< V
PG
-
3.5
0.80
6.2
1.0
9.0
V
k
t
PHLSENSE
(Figures 1, 2)
FN9039 Rev 5.00
December 3, 2015
Page 5 of 20
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