74LCX573 — Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
December 2013
74LCX573
Low Voltage Octal Latch with 5V Tolerant
Inputs and Outputs
Features
■
5V tolerant inputs and outputs
■
2.3V–3.6V V
CC
specifications provided
■
7.0 ns t
PD
max. (V
CC
= 3.3V), 10µA I
CC
max.
■
Power down high impedance inputs and outputs
■
Supports live insertion/withdrawal
(1)
■
±24mA output drive (V
CC
= 3.0V)
■
Implements
proprietary
noise/EMI reduction circuitry
■
Latch-up performance exceeds JEDEC 78 conditions
■
ESD performance
General Description
The LCX573 is a high-speed octal latch with buffered
common Latch Enable (LE) and buffered common Out-
put Enable (OE) input.
The LCX573 is functionally identical to the LCX373 but
has inputs and outputs on opposite sides.
The LCX573 is designed for low voltage applications
with capability of interfacing to a 5V signal environment.
The LCX573 is fabricated with an advanced CMOS
tech- nology to achieve high speed operation while
maintaining CMOS low power dissipation.
– Human body model
>
2000V
– Machine model
>
200V
■
Leadless DQFN package
Note:
1. To ensure the high impedance state during power up
or down, OE should be tied to V
CC
through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Order
Number
74LCX573WM
74LCX573SJ
74LCX573BQX
(2)
74LCX573MSA
74LCX573MTC
Package
Number
M20B
M20D
MLP20B
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.1
www.fairchildsemi.com
74LCX573 — Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Logic Symbol
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
V
CC
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
Truth Table
Inputs
OE
L
L
L
H
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition of
Latch Enable
Outputs
D
H
L
X
X
LE
H
H
L
X
O
n
H
L
O
0
Z
Pad Assignments for DQFN
OE V
CC
1
20
19
O
0
18
O
1
17
O
2
16
O
3
15
O
4
14
O
5
13
O
6
12
O
7
10
11
D
0
2
D
1
3
D
2
4
D
3
5
D
4
6
D
5
7
D
6
8
D
7
9
GND LE
Functional Description
(Bottom View)
The LCX573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode but this does not
interfere with entering new data into the latches.
(Top View)
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
DAP
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
No Connect
Description
Note: DAP (Die Attach Pad)
Logic Diagram
D
0
D
Q
D
1
D
Q
D
2
D
Q
D
3
D
Q
D
4
D
Q
D
5
D
Q
D
6
D
Q
D
7
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.1
www.fairchildsemi.com
2
74LCX573 — Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Conditions
Value
–0.5 to +7.0
–0.5 to +7.0
Units
V
V
V
mA
mA
mA
mA
mA
°C
Output in 3-STATE
Output in HIGH or LOW State
(3)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–50
–50
+50
±50
±100
±100
–65 to +150
Recommended Operating Conditions
(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
I
OH
/ I
OL
Parameter
Supply Voltage
Input Voltage
Output Voltage
Output Current
Conditions
Operating
Data Retention
HIGH or LOW State
3-STATE
V
CC
= 3.0V–3.6V
V
CC
= 2.7V–3.0V
V
CC
= 2.3V–2.7V
Min.
2.0
1.5
0
0
0
Max.
3.6
3.6
5.5
V
CC
5.5
±24
±12
±8
Units
V
V
V
mA
T
A
∆
t /
∆
V
Free-Air Operating Temperature
Input Edge Rate
V
IN
= 0.8V–2.0V, V
CC
= 3.0V
–40
0
85
10
°C
ns /V
Notes:
3. I
O
Absolute Maximum Rating must be observed.
4. Unused inputs must be held HIGH or LOW. They may not float.
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.1
www.fairchildsemi.com
3
74LCX573 — Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
DC Electrical Characteristics
T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output
Voltage
V
CC
(V)
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
2.7
3.0
Conditions
Min.
1.7
2.0
Max.
Units
V
0.7
0.8
I
OH
= –100µA
I
OH
= –8mA
I
OH
= –12mA
I
OH
= –18mA
I
OH
= –24mA
I
OL
= 100µA
I
OL
= 8mA
I
OL
= 12mA
I
OL
= 16mA
I
OL
= 24mA
0
≤
V
I
≤
5.5V
0
≤
V
O
≤
5.5V, V
I
= V
IH
or V
IL
V
I
or V
O
= 5.5V
V
I
= V
CC
or GND
3.6V
≤
V
I
, V
O
≤
5.5V
(5)
V
IH
= V
CC
–0.6V
V
CC
– 0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
±5.0
10
10
±10
500
V
V
V
OL
LOW Level Output
Voltage
2.3–3.6
2.3
2.7
3.0
V
I
I
I
OZ
I
OFF
I
CC
∆
I
CC
Input Leakage Current
3-STATE Output Leakage
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
2.3–3.6
2.3–3.6
0
2.3–3.6
2.3–3.6
µA
µA
µA
µA
µA
AC Electrical Characteristics
T
A
= –40°C to +85°C, R
L
= 500Ω
V
CC
= 3.3V ± 0.3V,
C
L
= 50pF
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
S
t
H
t
W
V
CC
= 2.7V,
C
L
= 50pF
Min.
1.5
1.5
1.5
1.5
2.5
1.5
3.3
V
CC
= 2.5 ± 0.2V,
C
L
= 30pF
Min.
1.5
1.5
1.5
1.5
4.0
2.0
4.0
Parameter
Propagation Delay, D
n
to O
n
Propagation Delay, LE to O
n
Output Enable Time
Output Disable Time
Setup Time, D
n
to LE
Hold Time, D
n
to LE
LE Pulse Width
Min.
1.5
1.5
1.5
1.5
2.5
1.5
3.3
Max.
8.0
8.5
8.5
6.5
Max.
9.0
9.5
9.5
7.0
Max.
9.6
10.5
10.5
7.8
Units
ns
ns
ns
ns
ns
ns
ns
ns
t
OSHL
, t
OSLH
Output to Output Skew
(6)
Notes:
5. Outputs disabled or 3-STATE only.
1.0
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.1
www.fairchildsemi.com
4
74LCX573 — Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
Dynamic Switching Characteristics
T
A
= 25°C
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
V
CC
(V)
3.3
2.5
3.3
2.5
Conditions
C
L
= 50pF, V
IH
= 3.3V, V
IL
= 0V
C
L
= 30pF, V
IH
= 2.5V, V
IL
= 0V
C
L
= 50pF, V
IH
= 3.3V, V
IL
= 0V
C
L
= 30pF, V
IH
= 2.5V, V
IL
= 0V
Typical
0.8
0.6
–0.8
–0.6
Units
V
V
Capacitance
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
V
CC
= Open, V
I
= 0V or V
CC
V
CC
= 3.3V, V
I
= 0V or V
CC
V
CC
= 3.3V, V
I
= 0V or V
CC
, f = 10 MHz
Typical
7
8
25
Units
pF
pF
pF
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.1
www.fairchildsemi.com
5
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