Preliminary
GS8342S08/09/18/36E-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with future 72Mb and 144Mb devices
36Mb Burst of 2
DDR SigmaSIO-II SRAM
167 MHz–333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
SigmaRAM™ Family Overview
GS8342S08/09/18/36 are built in compliance with the
SigmaSIO-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 2M x 18 has a 1M
addressable index).
Parameter Synopsis
- 333
tKHKH
tKHQV
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.02 8/2005
1/39
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8342S08/09/18/36E-333/300/250/200/167
1M x 36 SigmaQuad SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
D
OFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
/SA
(288Mb)
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC/SA
(72Mb)
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW1
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
V
SS
/SA
(144Mb)
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11 x 15 Bump BGA—15 x 17 mm
2
Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 72Mb, A10 for 144Mb, A2 for 288Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 1.02 8/2005
5/39
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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