128K x 36, 3.3V Synchronous
IDT71V546S
SRAM with ZBT™ Feature
™
Burst Counter and Pipelined Outputs
Features
◆
◆
◆
◆
◆
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control
OE
Single R/W (READ/WRITE) control pin
◆
◆
◆
◆
◆
◆
◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
Green parts available, see Ordering Information
Functional Block Diagram
LBO
Address A [0:16]
CE
1
, CE
2
,
CE
2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
128K x 36 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
3821 drw 01
.
DSC-3821/07
Data I/O [0:31], I/O P[1:4]
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
AUGUST 2017
1
©2017 Integrated Device Technology, Inc.
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
™
Commercial and Industrial Temperature Ranges
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBT
TM
,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when
CEN
is high and the internal device registers will hold their previous
values.
Description
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers (reads or writes) will be completed. The data bus will tri-state two
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the
LBO
input
pin. The
LBO
pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes a high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A
0
- A
16
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
- I/O
31
, I/O
P1
- I/O
P4
V
DD
V
SS
Address Inputs
Three Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3821 tbl 01
2
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
™
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
- A
16
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/LD Low,
CEN
Low and true
chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with
new address and control when it is sampled low at the rising edge of clock with
the chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identified whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
Synchrono us Clock Enable Input. When
CEN
is sampled high, all other
synchronous inputs, includ ing clock are ignored and outputs remain unchanged.
The effect of
CEN
samp led high on the device outputs is as if the low to high
clock transition did not occur. For normal operation,
CEN
must be sampled low
at rising edge of clock.
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/W and ADV/LD are sampled low)
the appropriate byte write signal (BW
1
-
BW
4
) must be valid. The byte write
signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written
into the device two cycles later.
BW
1
-
BW
4
can all be tied low if always doing
write to the entire 36-bit word.
Synchro nous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to
enable the IDT71V546. (CE
1
or
CE
2
sampled high or CE
2
sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.
Synchronout active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable
the chip. CE
2
has inverted polarity but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V546. Except for
OE,
all timing references for
the device are made with respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is
selected. When
LBO
is low the Linear burst sequence is selected.
LBO
is a
static DC input.
Asynchronous output enable.
OE
must be low to read data from the 71V546.
When
OE
is high the I/O pins are in a high-impedance state.
OE
does not need
to be actively controlled for read and write cycles. In normal operation,
OE
can
be tied low.
3.3V power supply input.
Ground pin.
3821 tbl 02
ADV/LD
Address/Load
I
N/A
R/W
Read/Write
I
N/A
CEN
Clock Enable
I
LOW
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE2
CLK
I/O
0
- I/O
31
I/O
P1 -
I/O
P4
LBO
Chip Enable
Clock
Data Input/Output
Linear Burst
Order
Output Enable
I
I
I/O
I
HIGH
N/A
N/A
LOW
OE
I
LOW
V
DD
V
SS
Power Supply
Ground
N/A
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
3
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
™
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K X 36
I/O
P2
I/O
15
I/O
14
V
DD
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DD
I/O
9
I/O
8
V
SS
V
DD
V
DD
V
SS
I/O
7
I/O
6
V
DD
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DD
I/O
1
I/O
0
I/O
P1
72
71
70
68
63
55
80
79
78
77
76
75
74
73
69
67
66
65
64
62
61
60
59
58
57
56
54
53
A
9
A
8
NC
NC
ADV/LD
OE
CEN
R/W
CLK
V
SS
V
DD
CE
2
BW
1
BW
2
BW
3
BW
4
CE
2
CE
1
A
7
A
6
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
1
2
3
4
5
6
7
8
9
52
51
71V546
PKG100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
18
19
20
21
22
23
24
25
26
27
28
29
30
A
16
A
15
A
14
A
13
A
12
A
11
A
10
NC
NC
V
DD
V
SS
NC
NC
A
0
A
1
A
2
A
3
A
4
A
5
LBO
14
15
16
17
NOTE:
1. Pin 14 does not have to be connected directly to V
DD
as long as the input voltage is > V
IH
.
I/O
P3
I/O
16
I/O
17
V
DD
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DD
I/O
22
I/O
23
V
DD
(1)
V
DD
V
DD
V
SS
I/O
24
I/O
25
V
DD
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DD
I/O
30
I/O
31
I/O
P4
3821 drw 02a
100 TQFP
Top View
iew
4
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
™
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Commercial
Operating Ambient
Temperature
Industrial
Operating Ambient
Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Commercial &
Industrial Values
-0.5 to +4.6
-0.5 to V
DD
+0.5
Unit
V
V
Recommended DC Operating
Conditions
Symbol
V
DD
(3)
V
SS
V
IH
Parameter
Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
0
2.0
2.0
-0.5
(1)
Typ.
3.3
0
____
____
____
Max.
3.465
0
4.6
V
DD
+0.3
(2)
0.8
Unit
V
V
V
V
V
3821 tbl 04
V
TERM
(3)
0 to +70
o
C
V
IH
V
IL
T
A
(4)
-40 to +85
-55 to +125
-55 to +125
2.0
50
o
C
C
C
T
BIAS
T
STG
P
T
I
OUT
o
o
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC/2
, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC/2
, once per cycle.
3. V
DD
needs to be ramped up smoothly to the operating level. If there are any
glitches on V
DD
that cause the voltage level to drop below 2.0 volts then the
device needs to be reset by holding V
DD
to 0.0 volts for a minimum of 100 ms.
W
mA
3821 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. V
DD
and Input terminals only.
3. I/O terminals.
4. During production testing, the case temperature equals the ambient temperature.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Ambient
Temperature
(1)
0
O
C to +70
O
C
-40
O
C to +85
O
C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
3821 tbl 03
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
100 TQFP Capacitance
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
3821 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
5
6.42
TI技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
