d. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequade bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 90 °C/W for both channels.
Document Number: 73629
S10-0547-Rev. B, 08-Mar-10
www.vishay.com
1
Si5509DC
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate Threshold Voltage
Gate-Body Leakage
V
DS
ΔV
DS
/T
J
ΔV
GS(th)
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, I
D
= - 250 µA
I
D
= 250 µA
I
D
= - 250 µA
I
D
= 250 µA
I
D
= - 250 µA
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= 0 V, V
GS
= ± 12 V
V
DS
= 20 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= - 20 V, V
GS
= 0 V
V
DS
= 20 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
= - 20 V, V
GS
= 0 V, T
J
= 55 °C
On-State Drain Current
b
I
D(on)
V
DS
≤
5 V, V
GS
= 4.5 V
V
DS
≤
- 5 V, V
GS
= - 4.5 V
V
GS
= 4.5 V, I
D
= 5.0 A
Drain-Source On-State Resistance
b
R
DS(on)
V
GS
= - 4.5 V, I
D
= - 3.9 A
V
GS
= 2.5 V, I
D
= 3.9 A
V
GS
= - 2.5 V, I
D
= - 2.9 A
Forward Transconductance
b
Dynamic
a
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
iss
C
oss
C
rss
P-Channel
V
DS
= - 10 V, V
GS
= 0 V, f = 1 MHz
V
DS
= 10 V, V
GS
= 5 V, I
D
= 4.0 A
Total Gate Charge
Q
g
V
DS
= - 10 V, V
GS
= - 5 V, I
D
= - 3.9 A
N-Channel
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.0 A
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Q
gs
Q
gd
R
g
P-Channel
V
DS
= - 10 V, V
GS
= - 4.5 V, I
D
= - 3.9 A
f = 1 MHz
N-Ch
N-Channel
V
DS
= 10 V, V
GS
= 0 V, f = 1 MHz
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
455
300
85
95
50
65
4.4
4.1
3.8
3.9
0.9
0.7
0.95
1.25
1.9
8
Ω
6.6
6.2
5.7
5.9
nC
pF
g
fs
V
DS
= 10 V, I
D
= 5.0 A
V
DS
= - 10 V, I
D
= - 3.9 A
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
10
- 15
0.043
0.074
0.068
0.128
10.4
8.2
0.052
0.090
0.084
0.160
S
Ω
0.7
- 0.7
20
- 20
18.4
- 15.1
- 3.4
2.2
2
-2
100
- 100
1
-1
10
- 10
A
µA
V
nA
mV/°C
V
Symbol
Test Conditions
Min.
Typ.
a
Max.
Unit
www.vishay.com
2
Document Number: 73629
S10-0547-Rev. B, 08-Mar-10
Si5509DC
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Dynamic
a
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
a
Symbol
Test Conditions
N-Ch
N-Channel
V
DD
= 10 V, R
L
= 2.5
Ω
I
D
≅
4.0 A, V
GEN
= 4.5 V, R
g
= 1
Ω
P-Channel
V
DD
= - 10 V, R
L
= 3.2
Ω
I
D
≅
- 3.14 A, V
GEN
= - 4.5 V, R
g
= 1
Ω
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
I
S
= 2.4 A, V
GS
= 0 V
I
S
= - 1.5 A, V
GS
= 0 V
N-Ch
P-Ch
N-Ch
P-Ch
N-Channel
I
F
= 2.4 A, dI/dt = 100 A/µs, T
J
= 25 °C
P-Channel
I
F
= - 1.5 A, dI/dt = - 100 A/µs, T
J
= 25 °C
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
Min.
Typ.
a
6
8
95
75
12
25
6
60
Max.
9
12
143
113
18
38
9
90
3.75
- 3.75
10
- 15
Unit
t
d(on)
t
r
t
d(off)
t
f
ns
I
S
I
SM
V
SD
t
rr
Q
rr
t
a
t
b
T
C
= 25 °C
A
0.8
- 0.8
12
18
5
8
7.5
14
4.5
4
1.2
- 1.2
18
27
8
12
V
ns
nC
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
