There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 1 is based on T
J(pk)
= 150_C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
≤
150_C. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less then
the limitations imposed by second breakdown.
4.0
6.0 8.0 10
20
40
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
60
Figure 1. Active−Region Safe Operating Area
hFE, DC CURRENT GAIN, NORMALIZED
10
7.0
5.0
3.0
2.0
2.0
150°C
T
J
= 25°C
V
CE
= 1.0 Vdc
VOLTAGE (VOLTS)
- 55°C
1.6
T
J
= 25°C
1.2
1.0
0.7
0.5
0.3
0.2
0.1
0.01
0.8
V
BE(sat)
@ I
C
/I
B
= 10
V
BE(on)
@ V
CE
= 1.0 V
0.4
V
CE(sat)
@ I
C
/I
B
= 10
0.02 0.03 0.05 0.1
0.2 0.3 0.5
1.0
I
C
, COLLECTOR CURRENT (AMP)
2.0 3.0 4.0
0
0.005 0.01 0.02 0.03 0.05 0.1
0.2 0.3 0.5
1.0
I
C
, COLLECTOR CURRENT (AMP)
2.0 3.0 4.0
Figure 2. DC Current Gain
Figure 3. “On” Voltage
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
1.0
0.7
0.5
0.3
0.2
D = 0.5
0.2
0.1
q
JC
(t) = r(t)
q
JC
q
JC
= 3.12°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
q
JC
(t)
P
(pk)
0.1
0.07
0.05
0.03
0.02
0.05
0.02
0.01
SINGLE PULSE
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1.0
2.0 3.0 5.0
10
t, TIME OR PULSE WIDTH (ms)
20
50
100
200
500
1000
Figure 4. Thermal Response
http://onsemi.com
2
MJE371G
PACKAGE DIMENSIONS
TO−225
CASE 77−09
ISSUE AC
4
1 2
3
FRONT VIEW
3 2
1
BACK VIEW
E
A1
Q
A
PIN 4
BACKSIDE TAB
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. NUMBER AND SHAPE OF LUGS OPTIONAL.
DIM
A
A1
b
b2
c
D
E
e
L
L1
P
Q
MILLIMETERS
MIN
MAX
2.40
3.00
1.00
1.50
0.60
0.90
0.51
0.88
0.39
0.63
10.60
11.10
7.40
7.80
2.04
2.54
14.50
16.63
1.27
2.54
2.90
3.30
3.80
4.20
D
P
1
2
3
L1
L
STYLE 1:
PIN 1. EMITTER
2., 4. COLLECTOR
3. BASE
2X
b2
2X
e
b
FRONT VIEW
c
SIDE VIEW
ON Semiconductor
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