74VHC573 Octal D-Type Latch with 3-STATE Outputs
May 2007
74VHC573
Octal D-Type Latch with 3-STATE Outputs
Features
■
High Speed: t
PD
=
5.0ns (Typ.) at V
CC
=
5V
■
High Noise Immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
■
Power Down Protection is provided on all inputs
■
Low Noise: V
OLP
=
0.6V (Typ.)
■
Low Power Dissipation: I
CC
=
4µA (Max.) @ T
A
=
25°C
■
Pin and function compatible with 74HC573
tm
General Description
The VHC573 is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while main-
taining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a latch enable input (LE)
and an Output Enable input (OE). When the OE input is
HIGH, the eight outputs are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Order Number
74VHC573M
74VHC573SJ
74VHC573MTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Description
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
©1993 Fairchild Semiconductor Corporation
74VHC573 Rev. 1.3
www.fairchildsemi.com
74VHC573 Octal D-Type Latch with 3-STATE Outputs
Logic Symbol
IEEE/IEC
Functional Description
The VHC573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW the latches store the information that
was present on the D inputs, a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode, but, this does
not interfere with entering new data into the latches.
Truth Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
n
H
L
O
0
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation
74VHC573 Rev. 1.3
www.fairchildsemi.com
2
74VHC573 Octal D-Type Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±75mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
Parameter
Rating
2.0V to +5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74VHC573 Rev. 1.3
www.fairchildsemi.com
3
74VHC573 Octal D-Type Latch with 3-STATE Outputs
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to +85°C
Max.
Min.
1.50
0.7 x V
CC
0.50
0.50
0.3 x V
CC
1.9
2.9
4.4
2.48
3.80
V
V
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0–5.5
2.0
3.0–5.5
2.0
3.0
4.5
3.0
4.5
Conditions
Min.
1.50
0.7 x V
CC
Typ.
Max.
Units
V
0.3 x V
CC
V
IN
=
V
IH
I
OH
=
–50µA
or V
IL
1.9
2.9
4.4
I
OH
=
–4mA
I
OH
=
–8mA
V
IN
=
V
IH
I
OL
=
50µA
or V
IL
2.58
3.94
0.0
0.0
0.0
I
OL
=
4mA
I
OL
=
8mA
V
IN
=
V
IH
or V
IL
,
V
OUT
=
V
CC
or GND
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
0.1
0.1
0.1
0.36
0.36
±0.25
±0.1
4.0
2.0
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
0.1
0.1
0.1
0.44
0.44
±2.5
±1.0
40.0
V
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage
Current
Quiescent Supply
Current
5.5
0–5.5
5.5
µA
µA
µA
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(2)
V
OLV(2)
V
IHD(2)
V
ILD(2)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
Typ.
0.9
–0.8
Limits
1.2
–1.0
3.5
1.5
Units
V
V
V
V
Note:
2. Parameter guaranteed by design.
©1993 Fairchild Semiconductor Corporation
74VHC573 Rev. 1.3
www.fairchildsemi.com
4
74VHC573 Octal D-Type Latch with 3-STATE Outputs
AC Electrical Characteristics
T
A
=
25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C
to +85°C
Max.
11.9
15.4
7.7
9.7
11.0
14.5
6.8
8.8
11.5
15.0
7.7
9.7
14.5
9.7
1.5
1.0
Parameter
Propagation Delay
Time (LE to O
n
)
V
CC
(V)
3.3 ± 0.3
5.0 ± 0.5
Conditions
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
R
L
=
1kΩ
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
R
L
=
1kΩ
(3)
Min.
Typ.
7.6
10.1
5.0
6.5
7.0
9.5
4.5
6.0
7.3
9.8
5.2
6.7
10.7
6.7
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
14.0
17.5
9.0
11.0
13.0
16.5
8.0
10.0
13.5
17.0
9.0
11.0
16.5
11.0
1.5
1.0
10
Units
ns
t
PLH
, t
PHL
Propagation Delay
Time (D–O
n
)
3.3 ± 0.3
5.0 ± 0.5
ns
t
PZL
, t
PZH
3-STATE Output
Enable Time
3.3 ± 0.3
5.0 ± 0.5
ns
t
PLZ
, t
PHZ
3-STATE Output
Disable Time
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
ns
ns
pF
pF
pF
t
OSLH
, t
OSHL
Output to Output
Skew
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
V
CC
=
Open
V
CC
=
5.0V
(4)
4
6
29
10
Notes:
3. Parameter guaranteed by design. t
OSLH
=
|t
PLH max
– t
PLH min
|; t
OSHL
=
|t
PHL max
– t
PHL min
|
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
I
CC
(Opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 8 (per Latch). The total C
PD
when n pcs. of the Latch operates can be
calculated by the equation: C
PD
(total)
=
21 + 8n.
AC Operating Requirements
V
CC
(V)
3.3 ± 0.3
5.0 ± 0.5
t
S
t
H
Minimum Setup Time
Minimum Hold Time
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
T
A
=
25°C
Min.
5.0
5.0
3.5
3.5
1.5
1.5
T
A
=
–40°C to
+85°C
Max.
Min.
5.0
5.0
3.5
3.5
1.5
1.5
ns
ns
Symbol
Parameter
Typ.
Max.
Units
ns
t
w
(H), t
w
(L) Minimum Pulse Width (LE)
©1993 Fairchild Semiconductor Corporation
74VHC573 Rev. 1.3
www.fairchildsemi.com
5
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