d. See Solder Profile (www.vishay.com/doc?73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not
plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
www.vishay.com
1
T
C
= 25 °C
T
C
= 70 °C
Maximum Power Dissipation
T
A
= 25 °C
T
A
= 70 °C
Operating Junction and Storage Temperature Range
SiE854DF
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a, b
Maximum Junction-to-Case (Drain Top)
t
≤
10 s
Steady State
Symbol
R
thJA
R
thJC
(Drain)
R
thJC
(Source)
Typical
20
0.8
2.2
Maximum
24
1
2.7
°C/W
Unit
Maximum Junction-to-Case (Source)
a, c
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 68 °C/W.
c. Measured at source pin (on the side of the package).
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
V
DS
ΔV
DS
/T
J
ΔV
GS(th)
/T
J
V
GS(th)
I
GSS
I
DSS
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= 0 V, V
GS
= ± 20 V
V
DS
= 100 V, V
GS
= 0 V
V
DS
= 100 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
≥
5 V, V
GS
= 10 V
V
GS
=
10 V, I
D
= 13.2 A
V
DS
= 15 V, I
D
= 13.2 A
2.5
100
120
- 10
4.4
± 100
1
10
0.0117
30
3100
250
95
50
16
13
1
15
10
30
10
0.0142
V
mV/°C
V
nA
µA
A
Ω
S
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
I
D(on)
On-State Drain Current
a
R
DS(on)
Drain-Source On-State Resistance
a
a
g
fs
Forward Transconductance
Dynamic
b
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
Total Gate Charge
Q
g
Q
gs
Gate-Source Charge
Q
gd
Gate-Drain Charge
R
g
Gate Resistance
t
d(on)
Turn-On Delay Time
t
r
Rise Time
t
d(off)
Turn-Off Delay Time
t
f
Fall Time
Drain-Source Body Diode Characteristics
I
S
Continuous Source-Drain Diode Current
I
SM
Pulse Diode Forward Current
a
V
SD
Body Diode Voltage
t
rr
Body Diode Reverse Recovery Time
Q
rr
Body Diode Reverse Recovery Charge
t
a
Reverse Recovery Fall Time
t
b
Reverse Recovery Rise Time
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %
b. Guaranteed by design, not subject to production testing.
25
V
DS
= 50 V, V
GS
= 0 V, f = 1 MHz
pF
75
nC
1.5
25
15
45
15
60
60
1.2
110
300
Ω
V
DS
= 50 V, V
GS
= 10 V, I
D
= 13.2 A
f = 1 MHz
V
DD
= 50 V, R
L
= 5
Ω
I
D
≅
10 A, V
GEN
= 10 V, R
g
= 1
Ω
ns
T
C
= 25 °C
I
S
= 10 A
0.8
70
195
56
14
A
V
ns
nC
ns
I
F
= 10 A, dI/dt = 100 A/µs, T
J
= 25 °C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
60
V
GS
= 10
V
thru 7
V
16
I
D
- Drain Current (A)
20
T
C
= - 55 °C
50
I
D
- Drain Current (A)
40
V
GS
= 6
V
30
12
8
T
C
= 25 °C
4
20
10
V
GS
= 4
V
0
0.0
V
GS
= 5
V
T
C
= 125 °C
0
0.4
0.8
1.2
1.6
2.0
0
1
2
3
4
5
6
V
DS
- Drain-to-Source
Voltage
(V)
V
GS
- Gate-to-Source
Voltage
(V)
Output Characteristics
0.0120
4000
Transfer Characteristics
R
DS(on)
- On-Resistance (Ω)
0.0118
C - Capacitance (pF)
3200
C
iss
0.0116
2400
0.0114
V
GS
= 10
V
1600
0.0112
800
C
oss
0.0110
0
10
20
30
40
50
60
0
C
rss
0
20
40
60
80
100
I
D
- Drain Current (A)
V
DS
- Drain-to-Source
Voltage
(V)
On-Resistance vs. Drain Current and Gate Voltage
10
I
D
= 13.2 A
V
GS
- Gate-to-Source
Voltage
(V)
8
R
DS(on)
- On-Resistance
(Normalized)
V
DS
= 50
V
2.2
2.0
1.8
I
D
= 13.2 A
Capacitance
V
GS
= 10
V
1.6
1.4
1.2
1.0
0.8
0.6
6
V
DS
=
80 V
4
2
0
0
10
20
30
40
50
60
0.4
- 50
- 25
0
25
50
75
100
125
150
Q
g
- Total Gate Charge (nC)
T
J
- Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
www.vishay.com
3
SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
100
0.030
I
D
= 13.2 A
0.025
R
DS(on)
- On-Resistance (Ω)
T
A
= 125 °C
0.020
I
S
- Source Current (A)
T
J
= 150 °C
10
T
J
= 25 °C
0.015
T
A
= 25 °C
0.010
0.005
1
0.0
0
0.2
0.4
0.6
0.8
1.0
1.2
4
5
6
7
8
9
10
V
SD
- Source-to-Drain
Voltage
(V)
V
GS
- Gate-to-Source
Voltage
(V)
Source-Drain Diode Forward Voltage
4.0
50
On-Resistance vs. Gate-to-Source Voltage
3.5
40
V
GS(th)
(V)
3.0
Po
w
er (
W
)
I
D
= 250
µA
30
2.5
20
2.0
10
1.5
- 50
- 25
0
25
50
75
100
125
150
0
0.01
0.1
1
Time (s)
10
100
1000
T
J
- Temperature (°C)
Threshold Voltage
100
Limited
by
R
DS(on)
*
Single Pulse Power, Junction-to-Ambient
100
us
10
I
D
- Drain Current (A)
1 ms
10 ms
1
100 ms
0.1
T
A
= 25 °C
Single Pulse
0.01
0.01
0.1
1s
10 s
BVDSS
DC
1
10
100
V
DS
- Drain-to-Source
Voltage
(V)
*
V
GS
> minimum
V
GS
at
which
R
DS(on)
is specified
Safe Operating Area, Junction-to-Ambient
www.vishay.com
4
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
150
Package Limited
Po
w
er Dissipation (
W
)
140
120
100
80
60
40
20
0
25
50
75
100
125
150
I
D
- Drain Current (A)
T
C
- Case Temperature (°C)
T
C
- Case Temperature (°C)
Current Derating*
Power Derating, Junction-to-Case
* The power dissipation P
D
is based on T
J(max)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
