MC100EP16VC
3.3V / 5V ECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
EN goes HIGH, it will force the Q
HG
LOW and the Q
HG
HIGH on the
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
and Q
HG
remains LOW and Q
HG
remains HIGH. The next positive
transition of the data input is not passed on to the data outputs under
these conditions. The Q
HG
and Q
HG
outputs remain in their disabled
state as long as the EN input is held HIGH. The EN input has no
influence on the Q output and the data input is passed on (inverted) to
this output whether EN is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
The V
BB
/D pin is internally dedicated and available for differential
interconnect. V
BB
/D may rebias AC coupled inputs. When used,
decouple V
BB
/D and V
CC
via a 0.01
mF
capacitor and limit current
sourcing or sinking to 1.5 mA. When not used, V
BB
/D should be left
open.
The 100 Series contains temperature compensation.
Features
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MARKING DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
KEP66
ALYW
G
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
KP66
ALYWG
G
DFN8
MN SUFFIX
CASE 506AA
1
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
310 ps Typical Prop Delay Q,
•
•
•
•
•
•
•
•
380 ps Typical Prop Delay QHG, QHG
Gain > 200
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−5.5
V
Open Input Default State
Q
HG
Output Will Default LOW with D Inputs Open or at V
EE
V
BB
Output
Pb−Free Packages are Available
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
August, 2008
−
Rev. 7
1
Publication Order Number:
MC10EP16VC/D
3G MG
G
4
MC100EP16VC
Table 1. PIN DESCRIPTION
Q
1
8
V
CC
D*
Q
D
2
7
Q
HG
Q
HG
, Q
HG
EN*
V
BB
/D
V
BB
/D
3
LEN
V
BB
EN
4
Q
OE
6
Q
HG
V
CC
V
EE
EP
5
V
EE
Pin
ECL Data Input
ECL Data Output
ECL High Gain Data Outputs
ECL Enable Input
Reference Voltage Output / ECL Data Input
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit. Elec-
trically connect to the most negative supply
(GND) or leave unconnected, floating open.
Function
LATCH
D
*Pins will default LOW when left open.
Figure 1. 8−Lead Pinout
(Top View)
and Logic
Diagram
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 1
Level 1
Level 1
Value
75 kW
N/A
> 4 kV
> 200 V
> 2 kV
Pb−Free Pkg
Level 1
Level 3
Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
167 Devices
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MC100EP16VC
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb
Pb−Free
(Note 2)
DFN8
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
8 SOIC
8 SOIC
8 SOIC
8 TSSOP
8 TSSOP
8 TSSOP
DFN8
DFN8
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
6
−6
6
−6
50
100
±
1.5
−40
to +85
−65
to +150
190
130
41 to 44
185
140
41 to 44
129
84
265
265
35 to 40
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power)
Table 4. 100EP DC CHARACTERISTICS, PECL
V
CC
= 3.3 V, V
EE
= 0 V (Note 3)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
Input HIGH Current
Input LOW Current
D
0.5
Min
27
2155
1305
2075
1355
1775
2.0
1890
Typ
37
2280
1400
Max
47
2405
1555
2420
1675
2045
3.3
150
0.5
Min
32
2155
1305
2075
1355
1775
2.0
1890
25°C
Typ
42
2280
1400
Max
52
2405
1555
2420
1675
2045
3.3
150
0.5
Min
34
2155
1305
2075
1355
1775
2.0
1890
85°C
Typ
44
2280
1400
Max
54
2405
1555
2420
1675
2045
3.3
150
Unit
mA
mV
mV
mV
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to
−2.2
V.
4. All loading with 50
W
to V
CC
−
2.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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MC100EP16VC
Table 5. 100EP DC CHARACTERISTICS, PECL
V
CC
= 5.0 V, V
EE
= 0 V (Note 6)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 8)
Input HIGH Current
Input LOW Current
D
0.5
Min
27
3855
3005
3775
3055
3475
2.0
3490
Typ
37
3980
3100
Max
47
4105
3255
4120
3375
3705
5.0
150
0.5
Min
32
3855
3005
3775
3055
3475
2.0
3490
25°C
Typ
42
3980
3100
Max
52
4105
3255
4120
3375
3705
5.0
150
0.5
Min
34
3855
3005
3775
3055
3475
2.0
3490
85°C
Typ
44
3980
3100
Max
54
4105
3255
4120
3375
3705
5.0
150
Unit
mA
mV
mV
mV
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +2.0 V to
−0.5
V.
7. All loading with 50
W
to V
CC
−
2.0 V.
8. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 6. 100EP DC CHARACTERISTICS, NECL
V
CC
= 0 V; V
EE
=
−5.5
V to
−3.0
V (Note 9)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 10)
Output LOW Voltage (Note 10)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 11)
Input HIGH Current
Input LOW Current
0.5
Min
27
−1145
−1995
−1225
−1945
−1525
−1425
V
EE
+ 2.0
Typ
37
−1020
−1900
Max
47
−895
−1745
−880
−1625
−1325
0.0
Min
32
−1145
−1995
−1225
−1945
−1525
−1425
V
EE
+ 2.0
25°C
Typ
42
−1020
−1900
Max
52
−895
−1745
−880
−1625
−1325
0.0
Min
34
−1145
−1995
−1225
−1945
−1525
−1425
V
EE
+ 2.0
85°C
Typ
44
−1020
−1900
Max
54
−895
−1745
−880
−1625
−1325
0.0
Unit
mA
mV
mV
mV
mV
mV
V
I
IH
I
IL
150
0.5
150
0.5
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with V
CC
.
10. All loading with 50
W
to V
CC
−
2.0 V.
11. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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4
MC100EP16VC
Table 7. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
=
−3.0
V to
−5.5
V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 12)
−40°C
Symbol
f
max
t
PLH
,
t
PHL
Characteristic
Maximum Frequency (Figure 2)
Propagation Delay
(Differential) Q
(Differential) QHG, QHG
(Single−Ended) Q
(Single−Ended) QHG, QHG
Setup Time
Hold Time
Duty Cycle Skew (Note 13)
RMS Random Clock Jitter (Figure 2)
Input Voltage Swing
(Differential Configuration)
Output Rise/Fall Times
(20%
−
80%)
HG
Q
Q
QHG, QHG
25
150
200
70
EN = L to D
EN =H to D
EN = L to D
EN =H to D
200
250
250
300
50
100
100
50
Min
Typ
>3
280
360
330
410
15
60
50
15
5.0
0.2
800
800
300
130
20
<1
1200
1200
400
220
25
150
250
80
350
450
400
500
250
300
300
350
50
100
100
50
Max
Min
25°C
Typ
>3
310
380
360
430
5
40
40
20
5.0
0.2
800
800
350
150
20
<1
1200
1200
450
240
25
150
250
100
400
500
450
550
275
325
325
375
50
100
100
50
Max
Min
85°C
Typ
>3
340
430
390
480
18
10
5
20
5.0
0.2
800
800
350
170
20
<1
1200
1200
500
270
425
525
475
575
Max
Unit
GHz
ps
t
S
t
H
t
SKEW
t
JITTER
V
PP
t
r
t
f
ps
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
−
2.0 V.
13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
900
800
V
OUTpp
(mV)
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
1
JITTER
OUT
ps (RMS)
É
ÉÉÉÉ É É É É É É É É É É É É É É
É
ÉÉÉÉ É É É É É É É É É É É É É É
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉ
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
Figure 2. F
max
/Jitter for QHG, QHG Output
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