AS4C64M16MD1
1 Gb (64M x 16 bit) 1.8v High Performance Mobile DDR SDRAM
Features
4 banks x 16M x 16 organization
-
Data Mask for Write Control (DM)
-
Four Banks controlled by BA0 & BA1
-
Programmable CAS Latency: 2, 3
-
Programmable Wrap Sequence: Sequential
or Interleave
-
Programmable Burst Length:
2, 4, 8 or 16 for Sequential Type
2, 4, 8 or 16 for Interleave Type
-
Automatic and Controlled Precharge Command
-
Power Down Mode
-
Auto Refresh and Self Refresh
-
Refresh Interval: 8192 cycles/64ms
-
Double Data Rate (DDR)
-
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
-
Differential clock inputs CLK and /CLK
-
Power Supply 1.7V - 1.95V
-
Drive Strength (DS) Option: Full, 1/2, 1/4, 1/8
-
Auto Temperature-Compensated Self Refresh
(Auto TCSR)
-
Partial-Array Self Refresh (PASR) Option: Full,
1/2, 1/4, 1/8, 1/16
-
Deep Power Down (DPD) mode
-
Operating Temperature Range
• Extended -25°C to 85°C
• Industrial -40°C to 85°C
-
60 ball FPBGA package
ALL PRODUCTS ROHS COMPLIANT
-
Description
The AS4C64M16MD1 is a four bank mobile DDR
DRAM organized as 4 banks x 16M x 16. It
achieves high speed data transfer rates by
employing a chip architecture that prefetches
multiple bits and then synchronizes the output data
to a system clock.
All of the control, address, circuits is synchronized
with the positive edge of an externally sup- plied
clock. I/O transactions are possible on both edges
of DQS.
Operating the four memory banks in an
interleaved fashion allows random access
operation to occur at a higher rate than is possible
with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length,
CAS latency and speed grade of the device.
Additionally, the device supports low power saving
features like PASR, Auto-TCSR, DPD as well as
options for different drive strength. It’s ideally suit-
able for mobile application.
-5
System Frequency (fCK)
Clock Cycle Time (tCK3)
Output data access Time
5
5
-6
Unit
MHz
ns
ns
200
MHz 166 MHz
6
5
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency
400Mbps
(max)
333Mbps
(max)
200
MHz (max)
166
MHz (max)
CAS Latency
3
3
t
RCD
(ns)
15
18
t
RP
(ns)
15
18
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
AS4C64M16MD1-5BCN
AS4C64M16MD1-5BIN
AS4C64M16MD1-6BCN
AS4C64M16MD1-6BIN
Confidential
Org
64M x
16
64M x
16
64M x
16
64M x
16
Temperature
Commercial -
25°C
to
85°C
Industrial -40°C to 85°C
Commercial -
25°C
to
85°C
Industrial -40°C to 85°C
-2-
Max Clock
(MHz)
200
MHz
200
MHz
166 MHz
166 MHz
Package
60-ball
FBGA
60-ball
FBGA
60-ball
FBGA
60-ball
FBGA
Rev.2.0 Aug 2017
AS4C64M16MD1
Signal Pin Description
Pin
CLK
CLK
CKE
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
—
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge.
In addition to the column address, A10 is used to invoke autoprecharge operation at the
end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0,
BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS
WE
A0 - A13
Input
Pulse
Input
Level
DQx
Input/
Output
Input
Level
Data Input/Output pins operate in the same manner as conventional DRAMs.
BA0,
BA1
LDQS,
UDQS
Level
—
Selects which bank is to be active.
Input/
Output
Level
—
Data Input/Output are synchronous edges of the DQS. LDQS for DQ0-DQ7, UDQS for
DQ8-DQ15. Active on both edges for data input/output. Center aligned to input data and
Edge aligned to output data.
UDM,
LDM
Input
Pulse
Active High In Write mode, DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high. If it’s high, LDM cor-
responds to DQ0-DQ7, and UDM corresponds to data on DQ8-DQ15.
Power and ground for the input buffers and the core logic.
VDD, VSS
VDDQ
VSSQ
Supply
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Confidential
-5-
Rev.2.0 Aug 2017
FPGA/CPLD
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