MC74AC259, MC74ACT259
8−Bit Addressable Latch
The MC74AC259/74ACT259 is a high−speed 8−bit addressable
latch designed for general purpose storage applications in digital
systems. It is a multifunctional device capable of storing single line
data in eight addressable latches, and also a 1−of−8 decoder and
demultiplexer with active HIGH outputs. The device also incorporates
an active LOW Common Clear for resetting all latches, as well as an
active LOW Enable. It is functionally identical to the ALS259 8−bit
addressable latch.
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•
•
•
•
•
•
•
Serial−to−Parallel Conversion
Eight Bits of Storage with Output of Each Bit Available
Random (Addressable) Data Entry
Active High Demultiplexing or Decoding Capability
Easily Expandable
Common Clear
Pb−Free Packages are Available
V
CC
16
MR
15
E
14
D
13
Q
7
12
Q
6
11
Q
5
10
Q
4
9
16
1
PDIP−16
N SUFFIX
CASE 648
16
1
SOIC−16
D SUFFIX
CASE 751B
16
1
SOEIAJ−16
M, MEL SUFFIX
CASE 966
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
1
A
0
2
A
1
3
A
2
4
Q
0
5
Q
1
6
Q
2
7
Q
3
8
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
A
0
A
1
A
2
E
D
MR Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Figure 2. Logic Symbol
MODE SELECT TABLE
E
L
H
L
H
MR
H
H
L
L
Mode
Addressable Latch
Memory
Active HIGH 8−Channel Demultiplexer
Clear
H = HIGH Voltage Level
L = LOW Voltage Level
©
Semiconductor Components Industries, LLC, 2005
1
November, 2005 − Rev. 6
Publication Order Number:
MC74AC259/D
MC74AC259, MC74ACT259
MODE SELECT−FUNCTION TABLE
Operating
Mode
Master Reset
Inputs
MR
L
L
L
L
•
•
•
L
H
H
H
H
•
•
•
H
E
H
L
L
L
•
•
•
L
H
L
L
L
•
•
•
L
D
X
d
d
d
•
•
•
d
X
d
d
d
•
•
•
d
A
0
X
L
H
L
•
•
•
H
X
L
H
L
•
•
•
H
A
1
X
L
L
H
•
•
•
H
X
L
L
H
•
•
•
H
A
2
X
L
L
L
•
•
•
H
X
L
L
L
•
•
•
H
Q
0
L
Q=d
L
L
•
•
•
L
q
0
Q=d
q
0
q
0
•
•
•
q
0
Q
1
L
L
Q=d
L
•
•
•
L
q
1
q
1
Q=d
q
1
•
•
•
q
1
Q
2
L
L
L
Q=d
•
•
•
L
q
2
q
2
q
2
Q=d
•
•
•
q
2
Outputs
Q
3
L
L
L
L
•
•
•
L
q
3
q
3
q
3
q
3
•
•
•
q
3
Q
4
L
L
L
L
•
•
•
L
q
4
q
4
q
4
q
4
•
•
•
q
4
Q
5
L
L
L
L
•
•
•
L
q
5
q
5
q
5
q
5
•
•
•
q
5
Q
6
L
L
L
L
•
•
•
L
q
6
q
6
q
6
q
6
•
•
•
q
6
Q
7
L
L
L
L
•
•
•
Q=d
q
7
q
7
q
7
q
7
•
•
•
Q=d
Demultiplex
(Active HIGH
Decoder when
D = H)
Store
(Do Nothing)
Addressable
Latch
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW−to−HIGH Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed
or cleared.
FUNCTIONAL DESCRIPTION
The MC74AC259/74ACT259 has four modes of
operation as shown in the Mode Selection Table. In the
addressable latch mode, data on the Data line (D) is written
into the addressed latch. The addressed latch will follow the
data input with all non−addressed latches remaining in their
previous states in the memory mode. All latches remain in
their previous state and are unaffected by the Data or
Address inputs.
In the one−of−eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other outputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the MC74AC/ACT259 as an addressable
latch, changing more than one bit of the address could
impose a transient wrong address. Therefore, this should
only be done while in the memory mode. The Mode Select
Function Table summarizes the operations of the
MC74AC/ACT259.
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MC74AC259, MC74ACT259
Q
7
Q
6
Q
5
MR
Q
4
A
2
A
1
Q
3
A
0
Q
2
D
E
Q
1
Q
0
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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MC74AC259, MC74ACT259
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
CC
or GND Current per Output Pin
Storage Temperature
Value
−0.5 to +7.0
−0.5 to V
CC
+0.5
−0.5 to V
CC
+0.5
±20
±50
±50
−65 to +150
Unit
V
V
V
mA
mA
mA
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
@ 3.0 V
t
r
, t
f
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
Output Current − Low
V
CC
@ 4.5 V
V
CC
@ 5.5 V
t
r
, t
f
T
J
T
A
I
OH
I
OL
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
ns/V
−
140
85
−24
24
°C
°C
mA
mA
ns/V
V
V
Unit
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74AC259, MC74ACT259
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
−
−
−
74AC
T
A
=−40°C to +85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
−
−
8.0
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
−75
80
V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
I
OUT
= −50
μA
V
*V
IN
= V
IL
or V
IH
−12 mA
I
OH
−24 mA
−24 mA
I
OUT
= 50
μA
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
Unit
Conditions
V
IL
V
V
OH
V
V
μA
mA
mA
μA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
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