IS49RL36160: 产品描述DRAM; 产品类别存储; 文件大小3MB，共115页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/

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IS49RL36160概述

DRAM

IS49RL36160规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	ISSI(芯成半导体)
产品种类 Product Category	DRAM

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576Mb: x18, x36 RLDRAM 3

Features

RLDRAM 3

IS49RL18320– 2 Meg x 18 x 16 Banks

IS49RL36160– 1 Meg x 36 x 16 Banks

Features

•

1066 MHz DDR operation (2133 Mb/s/ball data

rate)

•

76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock

frequency)

•

Organization

– 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)

– 16 banks

•

1.2V center-terminated push/pull I/O

•

2.5V V

EXT

, 1.35V V

, 1.2V V

DDQ

I/O

•

Reduced cycle time (

RC (MIN) = 8 - 12ns)

•

SDR addressing

•

Programmable READ/WRITE latency (RL/WL) and

burst length

•

Data mask for WRITE commands

•

x#)

and output data clocks (QK

x#)

•

On-die DLL generates CK edge-aligned data and

•

64ms refresh (128K refresh per 64ms)

168-ball FBGA package

or 60

matched impedance outputs

Integrated on-die termination (ODT)

Single or multibank writes

Extended operating range (200–1066 MHz)

READ training register

Multiplexed and non-multiplexed addressing capa-

bilities

•

Mirror function

•

Output driver and ODT calibration

•

JTAG interface (IEEE 1149.1-2001)

•

Clock cycle and

RC timing

– 0.93ns and

RC (MIN) = 8ns

(RL3-2133)

– 0.93ns and

RC (MIN) = 10ns

(RL3-2133)

– 1.07ns and

RC (MIN) = 8ns

(RL3-1866)

– 1.07ns and

RC (MIN) = 10ns

(RL3-1866)

– 1.25ns and

RC (MIN) = 8ns

(RL3-1600)

– 1.25ns and

RC (MIN) = 10ns

(RL3-1600)

– 1.25ns and

RC (MIN) = 12ns

(RL3-1600)

•

Con guration

-32 Meg x 18

- 16 Meg x 36

•

Operating Temperature

– Commercial (T

= 0° to +95°C)

– Industrial (T

= –40°C to +95°C)

•

Package

– 168-ball FBGA

– 168-ball FBGA (Pb-free)

•

Revision

Options

no ce. ISSI assumes no liability arising out of the applica on or use of any informa on, products or services described herein. Customers are advised to obtain the

latest version of this device speciﬁca on before relying on any published informa on and before placing orders for produ.ct

Integrated Silicon Solu on, Inc. does not recommend the use of any of its products in life support applica ons where the failure or malfunc on of the product can

reasonably be expected to cause failure of the life support system or to signiﬁcantly aﬀect its safety or eﬀec veness. Products are not authorized for use in such

applica ons unless Integrated Silicon Solu on, Inc. receives wri en assurance to its sa sfac on, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) poten al liability of Integrated Silicon Solu on, Inc is adequately protected under the circumstances

RLDRAM® is a registered trademark of Micron Technology, Inc.

Integrated Silicon Solution, Inc. - www.issi.com -

Rev. 00C

11/21/2014

576Mb: x18, x36 RLDRAM 3

Features

Contents

General Description ......................................................................................................................................... 8

General Notes .............................................................................................................................................. 8

State Diagram .................................................................................................................................................. 9

Functional Block Diagrams ............................................................................................................................. 10

Ball Assignments and Descriptions ................................................................................................................. 12

Package Dimensions ....................................................................................................................................... 16

Electrical Characteristics – I

Specifications .................................................................................................. 17

Electrical Specifications – Absolute Ratings and I/O Capacitance ..................................................................... 21

Absolute Maximum Ratings ........................................................................................................................ 21

Input/Output Capacitance .......................................................................................................................... 21

AC and DC Operating Conditions .................................................................................................................... 22

AC Overshoot/Undershoot Specifications .................................................................................................... 24

Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 27

Slew Rate Definitions for Differential Input Signals ...................................................................................... 29

ODT Characteristics ....................................................................................................................................... 30

ODT Resistors ............................................................................................................................................ 30

ODT Sensitivity .......................................................................................................................................... 32

Output Driver Impedance ............................................................................................................................... 33

Output Driver Sensitivity ............................................................................................................................ 35

Output Characteristics and Operating Conditions ............................................................................................ 36

Reference Output Load ............................................................................................................................... 39

Slew Rate Definitions for Single-Ended Output Signals ..................................................................................... 40

Slew Rate Definitions for Differential Output Signals ........................................................................................ 41

Speed Bin Tables ............................................................................................................................................ 42

AC Electrical Characteristics ........................................................................................................................... 44

Temperature and Thermal Impedance Characteristics ..................................................................................... 49

Command and Address Setup, Hold, and Derating ........................................................................................... 51

Data Setup, Hold, and Derating ....................................................................................................................... 57

Commands .................................................................................................................................................... 63

MODE REGISTER SET (MRS) Command ......................................................................................................... 64

Mode Register 0 (MR0) .................................................................................................................................... 65

RC ............................................................................................................................................................. 66

Data Latency .............................................................................................................................................. 66

DLL Enable/Disable ................................................................................................................................... 66

Address Multiplexing .................................................................................................................................. 66

Mode Register 1 (MR1) .................................................................................................................................... 68

Output Drive Impedance ............................................................................................................................ 68

DQ On-Die Termination (ODT) ................................................................................................................... 68

DLL Reset ................................................................................................................................................... 68

ZQ Calibration ............................................................................................................................................ 69

ZQ Calibration Long ................................................................................................................................... 70

ZQ Calibration Short ................................................................................................................................... 70

AUTO REFRESH Protocol ............................................................................................................................ 71

Burst Length (BL) ....................................................................................................................................... 71

Mode Register 2 (MR2) .................................................................................................................................... 73

READ Training Register (RTR) ..................................................................................................................... 73

WRITE Protocol .......................................................................................................................................... 75

WRITE Command .......................................................................................................................................... 75

Multibank WRITE ....................................................................................................................................... 76

READ Command ............................................................................................................................................ 76

Integrated Silicon Solution, Inc. - www.issi.com -

Rev. 00C

11/21/2014

576Mb: x18, x36 RLDRAM 3

Features

AUTO REFRESH Command

............................................................................................................................ 78

INITIALIZATION Operation

............................................................................................................................ 80

WRITE Operation ............................................................................................................................................... 83

READ Operation ................................................................................................................................................. 87

AUTO REFRESH Operation

.............................................................................................................................. 90

Multiplexed Address Mode ............................................................................................................................... 93

Data Latency in Multiplexed Address Mode

........................................................................................... 98

REFRESH Command in Multiplexed Address Mode

............................................................................ 98

Mirror Function ...................................................................................................................................................102

RESET Operation ................................................................................................................................................. 102

IEEE 1149.1 Serial Boundary Scan (JTAG)

.................................................................................................... 103

Disabling the JTAG Feature ......................................................................................................................... 103

Test Access Port (TAP) .................................................................................................................................. 103

TAP Controller ............................................................................................................................................... 104

Performing a TAP RESET .............................................................................................................................. 106

TAP Registers .................................................................................................................................................. 106

TAP Instruction Set ........................................................................................................................................ 107

Revision History .................................................................................................................................................. 114

Rev. C, Production – 12/12 ...........................................................................................................................114

Rev. B, Advance – 1/12 .................................................................................................................................. 114

Rev. A, Advance – 6/11 .................................................................................................................................. 115

Integrated Silicon Solution, Inc. - www.issi.com -

Rev. 00C

11/21/2014

576Mb: x18, x36 RLDRAM 3

Features

List of Figures

Figure 1: 576Mb RLDRAM 3 Part Numbers ..................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................... 9

Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 10

Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 11

Figure 5: 168-Ball FBGA ................................................................................................................................. 16

Figure 6: Single-Ended Input Signal ............................................................................................................... 23

Figure 7: Overshoot ....................................................................................................................................... 24

Figure 8: Undershoot .................................................................................................................................... 24

Figure 9: V

for Differential Signals ................................................................................................................ 25

Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 26

Figure 11: Definition of Differential AC Swing and

DVAC ................................................................................ 26

Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 28

Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 29

Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 30

Figure 15: Output Driver ................................................................................................................................ 33

Figure 16: DQ Output Signal .......................................................................................................................... 38

Figure 17: Differential Output Signal .............................................................................................................. 39

Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39

Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40

Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41

Figure 21: Example Temperature Test Point Location ...................................................................................... 50

Figure 22: Nominal Slew Rate and

VAC for

IS (Command and Address - Clock) ............................................... 53

Figure 23: Nominal Slew Rate for

IH (Command and Address - Clock) ............................................................ 54

Figure 24: Tangent Line for

IS (Command and Address - Clock) ...................................................................... 55

Figure 25: Tangent Line for

IH (Command and Address - Clock) ..................................................................... 56

Figure 26: Nominal Slew Rate and

VAC for

DS (DQ - Strobe) .......................................................................... 59

Figure 27: Nominal Slew Rate for

DH (DQ - Strobe) ........................................................................................ 60

Figure 28: Tangent Line for

DS (DQ - Strobe) ................................................................................................. 61

Figure 29: Tangent Line for

DH (DQ - Strobe) ................................................................................................ 62

Figure 30: MRS Command Protocol ............................................................................................................... 64

Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 65

Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 68

Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 70

Figure 34: Read Burst Lengths ........................................................................................................................ 72

Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 73

Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 74

Figure 37: WRITE Command ......................................................................................................................... 75

Figure 38: READ Command ........................................................................................................................... 77

Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 78

Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 79

Figure 41: Power-Up/Initialization Sequence ................................................................................................. 81

Figure 42: WRITE Burst ................................................................................................................................. 83

Figure 43: Consecutive WRITE Bursts ............................................................................................................. 84

Figure 44: WRITE-to-READ ............................................................................................................................ 84

Figure 45: WRITE - DM Operation .................................................................................................................. 85

Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 86

Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 86

Figure 48: Basic READ Burst .......................................................................................................................... 87

Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 88

Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 88

Integrated Silicon Solution, Inc. - www.issi.com -

Rev. 00C

11/21/2014

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