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MC68030RC20C: 产品描述Microprocessors - MPU 32B ON-CHIP CACHE MMU; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小520KB，共36页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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MC68030RC20C概述

Microprocessors - MPU 32B ON-CHIP CACHE MMU

MC68030RC20C规格参数

参数名称	属性值
是否Rohs认证	符合
零件包装代码	PGA
包装说明	LEAD FREE, PGA-128
针数	128
Reach Compliance Code	unknown
ECCN代码	EAR99
Is Samacsys	N
地址总线宽度	32
位大小	32
边界扫描	NO
最大时钟频率	20 MHz
外部数据总线宽度	32
格式	FIXED POINT
集成缓存	YES
JESD-30 代码	S-CPGA-P128
长度	34.545 mm
低功率模式	NO
端子数量	128
最高工作温度	70 °C
最低工作温度
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	PGA
封装等效代码	PGA128,13X13
封装形状	SQUARE
封装形式	GRID ARRAY
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	5 V
认证状态	Not Qualified
座面最大高度	4.7 mm
速度	20 MHz
最大供电电压	5.25 V
最小供电电压	4.75 V
标称供电电压	5 V
表面贴装	NO
技术	HCMOS
温度等级	COMMERCIAL
端子形式	PIN/PEG
端子节距	2.54 mm
端子位置	PERPENDICULAR
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	34.545 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR
Base Number Matches	1

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Freescale Semiconductor, Inc.

MOTOROLA

Order this document

by MC68EC030/D

SEMICONDUCTOR

TECHNICAL DATA

MC68EC030

Technical Summary

Second-Generation 32-Bit Enhanced Embedded

Controller

The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for

the requirements of embedded control applications. The MC68EC030 is optimized to maintain

performance while using cost-effective memory subsystems. The rich instruction set and addressing

mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear

migration path for M68000 systems. The main features of the MC68EC030 are as follows:

•

Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors

Burst-Mode Bus Interface for Efficient DRAM Access

On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)

Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices

25- and 40-MHz Operating Frequency (up to 9.2 MIPS)

Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

Freescale Semiconductor, Inc...

Additional features of the MC68EC030 include:

•

Complete 32-Bit Nonmultiplexed Address and Data Buses

Sixteen 32-Bit General-Purpose Data and Address Registers

Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

Pipelined Architecture with Increased Parallelism Allows:

– Internal Caches Accesses in Parallel with Bus Transfers

– Overlapped Instruction Execution

Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),

Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

Complete Support for Coprocessors with the M68000 Coprocessor Interface

Internal Status Indication for Hardware Emulation Support

4-Gbyte Direct Addressing Range

Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density

NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

•

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

©MOTOROLA INC., 1991

For More Information On This Product,

Go to: www.freescale.com

µ MOTOROLA

Rev. 1

Freescale Semiconductor, Inc.

INTRODUCTION

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer

unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on

one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the

32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor

interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated

controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with

accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030

as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from

external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to

the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-

chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four

long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can

reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used

to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the

average access time for operand fetches is minimized.

The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)

memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the

MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure

1) provides the precise clock signals required to efficiently control memory subsystems, eliminating

system design constraints due to clock generation and distribution.

CONTROLLER

CLOCK (40 MHz)

Freescale Semiconductor, Inc...

20 MHz

OSC.

MC88916

MC68EC030

(40 MHz)

BUS CLOCK

(20 MHz)

BUS CLOCK

(40 MHz)

BUS CLOCK

(80 MHz)

Figure 1.

MC68EC030 Clock Circuitry

The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the

autonomous nature of these blocks. The bus controller consists of the address and data pads, the

multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus

cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.

Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the

micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing

MC68EC030 TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

MC68030RC20C相似产品对比

	MC68030RC20C	MC68030RC33C	MC68030CRC25C	MC68030RC25C	MC68EC030FE25C	MC68030RC50C	MC68EC030CFE25C	MC68030FE33C	MC68030CRC33C
描述	Microprocessors - MPU 32B ON-CHIP CACHE MMU	Microprocessors - MPU 32B ON-CHIP CACHE MMU	Microprocessors - MPU 32B ON-CHIP CACHE MMU	Microprocessors - MPU 32B ON-CHIP CACHE MMU	Microprocessors - MPU 32B ON-CHIP CACHE	Microprocessors - MPU 32B ON-CHIP CACHE MMU	Microprocessors - MPU 32B ON-CHIP CACHE	Microprocessors - MPU 32B ON-CHIP CACHE MMU	Microprocessors - MPU 32B ON-CHIP CACHE MMU
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合	符合
零件包装代码	PGA	PGA	PGA	PGA	QFP	PGA	QFP	QFP	PGA
包装说明	LEAD FREE, PGA-128	LEAD FREE, PGA-128	LEAD FREE, PGA-128	LEAD FREE, PGA-128	QFP,	LEAD FREE, PGA-128	QFP,	QFP, QFP132,1.2SQ	LEAD FREE, PGA-128
针数	128	128	128	128	132	128	132	132	128
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	3A991	EAR99
地址总线宽度	32	32	32	32	32	32	32	32	32
位大小	32	32	32	32	32	32	32	32	32
边界扫描	NO	NO	NO	NO	NO	NO	NO	NO	NO
最大时钟频率	20 MHz	33 MHz	25 MHz	25 MHz	25 MHz	50 MHz	25 MHz	33 MHz	33 MHz
外部数据总线宽度	32	32	32	32	32	32	32	32	32
格式	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
集成缓存	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 代码	S-CPGA-P128	S-CPGA-P128	S-CPGA-P128	S-CPGA-P128	S-CQFP-G132	S-CPGA-P128	S-CQFP-G132	S-CQFP-G132	S-CPGA-P128
长度	34.545 mm	34.545 mm	34.545 mm	34.545 mm	24.13 mm	34.545 mm	24.13 mm	24.13 mm	34.545 mm
低功率模式	NO	NO	NO	NO	NO	NO	NO	NO	NO
端子数量	128	128	128	128	132	128	132	132	128
最高工作温度	70 °C	70 °C	85 °C	70 °C	70 °C	70 °C	85 °C	70 °C	85 °C
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	PGA	PGA	PGA	PGA	QFP	PGA	QFP	QFP	PGA
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	FLATPACK	GRID ARRAY	FLATPACK	FLATPACK	GRID ARRAY
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	260	NOT SPECIFIED	260	260	NOT SPECIFIED
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	4.7 mm	4.7 mm	4.7 mm	4.7 mm	3.175 mm	4.7 mm	3.175 mm	3.175 mm	4.7 mm
速度	20 MHz	33 MHz	25 MHz	25 MHz	25 MHz	50 MHz	25 MHz	33 MHz	33 MHz
最大供电电压	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
最小供电电压	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	NO	NO	NO	YES	NO	YES	YES	NO
技术	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
端子形式	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	GULL WING	PIN/PEG	GULL WING	GULL WING	PIN/PEG
端子节距	2.54 mm	2.54 mm	2.54 mm	2.54 mm	0.635 mm	2.54 mm	0.635 mm	0.635 mm	2.54 mm
端子位置	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	QUAD	PERPENDICULAR	QUAD	QUAD	PERPENDICULAR
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	40	NOT SPECIFIED	40	40	NOT SPECIFIED
宽度	34.545 mm	34.545 mm	34.545 mm	34.545 mm	24.13 mm	34.545 mm	24.13 mm	24.13 mm	34.545 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
厂商名称	-	-	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)

MC68030RC20C

MC68030RC20C在线购买

MC68030RC20C概述

MC68030RC20C规格参数

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