CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379
for details.
5. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by transconductance or r
DS(ON)
and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
DC Electrical Specifications
V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over
the operating junction temperature range, -40°C to +125°C.
T
J
= +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
J
= -40°C to +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
POWER SUPPLY
Voltage Range
V
DD
Quiescent Current
V
DD
I
DD
INx = GND
INA = INB = 1MHz, square wave
-
-
-
-
5
25
-
-
4.5
-
-
16
-
-
V
mA
mA
UnderVoltage
V
DD
Undervoltage Lock-out
(Note 9, Figure 9)
Hysteresis
V
UV
INA = INB = True (Note 10)
-
-
3.3
~25
-
-
-
-
-
-
V
mV
INPUTs (Note 11)
Input Range for INA, INB
Logic 0 Threshold
for INA, INB (Note 9)
Logic 1 Threshold
for INA, INB (Note 9)
Input Capacitance of
INA, INB (Note 8)
V
IN
V
IL
Option A, nominally 37% x 3.3V
Option B, nominally 37% x 5.0V
V
IH
Option A, nominally 63% x 3.3V
Option B, nominally 63% x 5.0V
C
IN
-
-
-
-
-
-
-
1.22
1.85
2.08
3.15
2
-
-
-
-
-
-
GND
1.12
1.70
1.98
3.00
-
V
DD
1.32
2.00
2.18
3.30
-
V
V
V
V
V
pF
4
FN7719.3
February 20, 2013
ISL89160, ISL89161, ISL89162
DC Electrical Specifications
V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over
the operating junction temperature range, -40°C to +125°C. (Continued)
T
J
= +25°C
PARAMETERS
Input Bias Current
for INA, INB
SYMBOL
I
IN
TEST CONDITIONS
GND < V
IN
< V
DD
MIN
-
TYP
-
MAX
-
T
J
= -40°C to +125°C
MIN
(Note 7)
-10
MAX
(Note 7)
+10
UNITS
µA
OUTPUTS
High Level Output Voltage
Low Level Output Voltage
Peak Output Source Current
Peak Output Sink Current
NOTES:
7. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
9. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9
10. The true state of a specific part number is defined by the input logic symbol.
11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted
inputs is less than the logic 0 threshold voltage.
V
OHA
V
OHB
V
OLA
V
OLB
I
O
I
O
V
O
(initial) = 0V, C
LOAD
= 10nF
V
O
(initial) = 12V, C
LOAD
= 10nF
-
-
-
-
-
-
-6
+6
-
-
-
-
V
DD
- 0.1
GND
-
-
V
DD
GND + 0.1
-
-
V
V
A
A
AC Electrical Specifications
V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits apply over
the operating junction temperature range, -40°C to +125°C.
T
J
= +25°C
PARAMETERS
Output Rise Time (see Figure 4)
Output Fall Time (see Figure 4)
Output Rising Edge Propagation Delay for
Non-Inverting Inputs (see Figure 3)
Output Rising Edge Propagation Delay with Inverting
Inputs (see Figure 3)
Output Falling Edge Propagation Delay with
Non-Inverting Inputs (see Figure 3)
Output Falling Edge Propagation Delay with Inverting
PCB设计
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