GS840H18/32/36AT/B-180/166/150/1
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP or 119-Bump BGA package
• Pb-Free 100-lead TQFP package available
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
180 MHz–100 M
3.3 V V
3.3 V and 2.5 V I
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. T
burst function need not be used. New addresses can be load
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled b
the user via the FT mode pin/bump (pin 14 in the TQFP an
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output dat
bypass the Data Output Register. Holding FT high places th
RAM in Pipelined mode, activating the rising-edge-triggere
Data Output Register.
Functional Description
Applications
The GS840H18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840H18/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
SCD Pipelined Reads
The GS840H18/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAM
begin turning off their outputs immediately after the desele
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enab
(BW) input combined with one or more individual byte wri
signals (Bx). In addition, Global Write (GW) is available fo
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS840H18/32/36A operates on a 3.3 V power supply a
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separat
output power (V
DDQ
) pins are used to de-couple output noi
from the internal circuit.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
t
KQ
tCycle
I
DD
–180
5.5 ns
3.0 ns
335 mA
8 ns
9 ns
210 mA
–166
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
–150
6.6 ns
3.8 ns
280 mA
10 ns
12 ns
165 mA
–100
10 ns
4.5 ns
190 mA
12 ns
15 ns
135 mA
Rev: 1.11 10/2004
1/30
© 1999, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AT/B-180/166/150/1
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/’s; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.11 10/2004
5/30
© 1999, GSI Techno
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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