CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. The V
DD
and SDA pins should not be subjected to negative voltage while the V
BAT
pin is biased, otherwise latchup can result. See the
Applications section.
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a negative pulse limited to -0.5V.
DC Operating Characteristics – RTC
Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
V
DD
V
BAT
I
DD1
PARAMETER
Main Power Supply
Battery Supply Voltage
Supply Current
V
DD
= 5V
V
DD
= 3V
I
DD2
I
DD3
I
BAT
I
LI
I
LO
V
TRIP
V
TRIPHYS
V
BATHYS
IRQ/F
OUT
V
OL
Output Low Voltage
V
DD
= 5V
I
OL
= 3mA
V
DD
= 2.7V
I
OL
= 1mA
0.4
0.4
V
V
Supply Current With I
2
C Active
Supply Current (Low Power Mode)
Battery Supply Current
Input Leakage Current on SCL
I/O Leakage Current on SDA
V
BAT
Mode Threshold
V
TRIP
Hysteresis
V
BAT
Hysteresis
1.6
10
15
V
DD
= 5V
V
DD
= 5V, LPMODE = 1
V
BAT
= 3V
5, 6
5
5
5, 6
CONDITIONS
NOTES
MIN
(Note 9)
2.7
1.8
2
1.2
40
1.4
400
100
100
2.2
30
50
2.6
75
100
TYP
(Note 8)
MAX
(Note 9)
5.5
5.5
6
4
120
5
950
UNITS
V
V
µA
µA
µA
µA
nA
nA
nA
V
mV
mV
Power-Down Timing
Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
V
DD SR-
PARAMETER
V
DD
Negative Slewrate
CONDITIONS
NOTES
7
MIN
(Note 9)
TYP
(Note 8)
MAX
(Note 9)
10
UNITS
V/ms
Serial Interface Specifications
SYMBOL
V
IL
PARAMETER
Over the recommended operating conditions unless otherwise specified.
TEST CONDITIONS
NOTES
MIN
TYP
MAX
(Note 9) (Note 8) (Note 9)
-0.3
0.3 x
V
DD
UNITS
V
SERIAL INTERFACE SPECS
SDA and SCL Input Buffer LOW
Voltage
FN8085 Rev 8.00
September 12, 2008
Page 4 of 24
ISL1208
Serial Interface Specifications
SYMBOL
V
IH
Hysteresis
V
OL
C
PIN
f
SCL
t
IN
t
AA
t
BUF
PARAMETER
SDA and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
DD
, until
SDA exits the 30% to 70% of V
DD
window.
1300
T
A
= +25°C, f = 1MHz, V
DD
= 5V, V
IN
= 0V,
V
OUT
= 0V
10, 11
Over the recommended operating conditions unless otherwise specified.
(Continued)
TEST CONDITIONS
NOTES
MIN
TYP
MAX
(Note 9) (Note 8) (Note 9)
0.7 x
V
DD
0.05 x
V
DD
0
0.4
10
400
50
900
V
DD
+
0.3
UNITS
V
V
V
pF
kHz
ns
ns
ns
Time the Bus Must Be Free Before SDA crossing 70% of V
DD
during a STOP
the Start of a New Transmission
condition, to SDA crossing 70% of V
DD
during the following START condition.
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
DD
.
From SDA falling edge crossing 30% of V
DD
to SCL falling edge crossing 70% of V
DD
.
From SDA exiting the 30% to 70% of V
DD
window, to SCL rising edge crossing 30% of
V
DD
From SCL falling edge crossing 30% of V
DD
to SDA entering the 30% to 70% of V
DD
window.
From SCL rising edge crossing 70% of V
DD
,
to SDA rising edge crossing 30% of V
DD
.
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
DD
.
From SCL falling edge crossing 30% of V
DD
,
until SDA enters the 30% to 70% of V
DD
window.
From 30% to 70% of V
DD
From 70% to 30% of V
DD
10, 11
10, 11
10, 11
10, 11
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
1300
600
600
600
100
ns
ns
ns
ns
ns
t
HD:DAT
Input Data Hold Time
20
900
ns
t
SU:STO
t
HD:STO
t
DH
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
600
600
0
ns
ns
ns
t
R
t
F
Cb
Rpu
SDA and SCL Rise Time
SDA and SCL Fall Time
20 +
0.1 x Cb
20 +
0.1 x Cb
10
1
300
300
400
ns
ns
pF
k
Capacitive Loading of SDA or SCL Total on-chip and off-chip
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2k to~2.5k.
For Cb = 40pF, max is about 15kto ~20k
NOTES:
5. IRQ and F
OUT
Inactive.
6. LPMODE = 0 (default).
7. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
8. Typical values are for T = +25°C and 3.3V supply voltage.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Parameter is not 100% tested.
11. These are I
2
C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
NXP MCU
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