GS84118T/B-166/150/133/100
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (Pentium
TM
and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA:
T:TQFP or B: BGA
-166
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
t
cycle
t
KQ
I
DD
t
KQ
t
cycle
I
DD
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
-150
6.6 ns
3.8 ns
275 mA
10 ns
10 ns
190 mA
-133
7.5 ns
4.0 ns
250 mA
11 ns
15 ns
140 mA
-100
10 ns
4.5 ns
190 mA
12 ns
15 ns
140 mA
256K x 18 Sync
Cache Tag
166 MHz–100 MHz
8.5 ns–12 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT
mode pin, I/O registers can be programmed to perform pipeline
or flow through operation. Flow Through mode reduces
latency.
Byte write operation is performed by using Byte Write Enable
(BWE) input combined with two individual byte write signals
BW1-2. In addition, Global Write (GW) is available for
writing all bytes at one time.
Compare cycles begin as a read cycle with output disabled so
that compare data can be loaded into the data input register.
The comparator compares the read data with the registered
input data and a match signal is generated. The match output
can be either in Pipeline or Flow Through modes controlled by
the FT signal.
Low power (Standby mode) is attained through the assertion of
the ZZ signal, or by stopping the clock (CLK). Memory data is
retained during Standby mode.
JTAG boundary scan interface is provided using IEEE
standard 1149.1 protocol. Four pins—Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS)—are used to perform JTAG function.
The GS84118 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate
output (V
DDQ
) pins are used to allow both 3.3 V or 2.5 V IO
interface.
Functional Description
The GS84118 is a 256K x 18 high performance synchronous
SRAM with integrated Tag RAM comparator. A 2-bit burst
counter is included to provide burst interface with Pentium
TM
and other high performance CPUs. It is designed to be used as
a Cache Tag SRAM, as well as data SRAM. Addresses, data
IOs, match output, chip enables (CE1, CE2, CE3), address
control inputs (ADSP, ADSC, ADV), and write control inputs
(BW1, BW2, BWE, GW, DE) are synchronous and are
controlled by a positive-edge-triggered clock (CLK).
Output Enable (OE), Match Output Enable, and power down
control (ZZ) are asynchronous. Burst can be initiated with
either ADSP or ADSC inputs. Subsequent burst addresses are
generated internally and are controlled by ADV. The burst
sequence is either interleave order (Pentium
TM
or x86) or
linear order, and is controlled by LBO.
Rev: 1.05 7/2001
1/30
* Pentium is a trademark of Intel Corp.
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS84118T/B-166/150/130/100
Pin Configuration
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
9
DQ
10
V
SS
V
DDQ
DQ
11
DQ
12
FT
V
DD
NC
V
SS
DQ
13
DQ
14
V
DDQ
V
SS
DQ
15
DQ
16
DQ
P2
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
A
10
NC
NC
V
DDQ
V
SS
NC
DQ
P1
DQ
8
DQ
7
V
SS
VDDQ
DQ
6
DQ
5
V
SS
NC
V
DD
ZZ
DQ
4
DQ
3
V
DDQ
V
SS
DQ
2
DQ
1
NC
NC
V
SS
V
DDQ
MATCH
DE
MOE
Rev: 1.05 7/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
3
A
2
A
1
A
0
TMS
TDI
V
SS
V
DD
TDO
TCK
A
15
A
14
A
13
A
12
A
11
A
16
A
17
2/30
© 1999, Giga Semiconductor, Inc.
LBO
A
5
A
4
GS84118T/B-166/150/130/100
84118 PadOut
119-Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B1
NC
V
DDQ
NC
DQ
B4
V
DDQ
NC
DQ
B6
V
DDQ
DQ
B8
NC
NC
NC
V
DDQ
2
A
6
E
2
A
5
NC
DQ
B2
NC
DQ
B3
NC
V
DD
DQ
B5
NC
DQ
B7
NC
DQ
P2
A
2
A
10
TMS
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
11
TDI
4
ADSP
ADSC
V
DD
NC
E
1
G
ADV
GW
V
DD
CK
NC
BW
A
1
A
0
V
DD
NC
NC
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
12
TDO
6
A
9
E
3
A
16
DQ
P1
NC
DQ
A7
NC
DQ
A5
V
DD
NC
DQ
A3
MATCH
DQ
A2
MOE
A
13
A
17
TCK
7
V
DDQ
NC
NC
NC
DQ
A8
V
DDQ
DQ
A6
NC
V
DDQ
DQ
A4
NC
V
DDQ
DE
DQ
A1
NC
ZZ
V
DDQ
Rev: 1.05 7/2001
3/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
TQFP Pin Description
Pin Location
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48,
47, 46, 45, 44, 49, 50
89
87
93
94
88
92, 97, 98
86
83
84, 85
58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18,
19, 22, 23
74, 24
53
51
52
64
14
31
38
39
42
43
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71,
76, 90
4, 11, 20, 27, 54, 61, 70, 77
1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75,
78, 79, 95, 96
Symbol
A0–A17
CLK
BWE
BW1
BW2
GW
CE1,CE2, CE3
OE
ADV
ADSP, ADSC
DQ1–DQ16
DQP1–DQP2
MATCH
MOE
DE
ZZ
FT
LBO
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
NC
Description
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on
page 11.
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal
needs to be combined with one of the four byte write signals
for a write operation to occur.
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data outputs 9 thru 16
Global Write Enable
Chip Enables
Output Enable
Burst address advance
Address status signals
Data Input and Output pins
Parity Input and Output pins
Match Output
Match Output Enable
Data Enable—Data input registers are updated only when DE
is active.
Power down control—Application of ZZ will result in a low
standby power consumption.
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
Test Data Out
Test Clock
3.3 V power supply
Ground
2.5 V/3.3 V output power supply
No Connect
Rev: 1.05 7/2001
4/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
PBGA Pin Description
Pin Location
P4, N4, R2, C3, B3, C2, A2, A3, A5, A6, T6, C5,
R6, T5, T2, T3, B5, C6
K4
M4
L5
G3
H4
E4, B2, B6
F4
G4
A4, B4
P7, N6, L6, K7, H6, G7, F6, E7, D1, E2, G2, H1,
K2, L1, M2, N1
D6, P2
M6
P6
N7
T7
R5
R3
U2
U3
U5
U4
C4, J2, J4, J6, R4
D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5,
N3, N5, P3, P5
A1, A7, F1, F7, J1, J7, M1, M7, U1, U7
B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5,
G6, H2, H7, J3, J5, K1, K6, L2, L3, L4, L7, N2,
P1, RR1, R7, T1, T4, U6
Symbol
A0–A17
CLK
BWE
BW1
BW2
GW
CE1,CE2, CE3
OE
ADV
ADSP, ADSC
DQ1–DQ16
DQP1–DQP2
MATCH
MOE
DE
ZZ
FT
LBO
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
NC
Description
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on
page 11.
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal needs to
be combined with one of the four byte write signals for a write
operation to occur.
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data outputs 9 thru 16
Global Write Enable
Chip Enables
Output Enable
Burst address advance
Address status signals
Data Input and Output pins
Parity Input and Output pins
Match Output
Match Output Enable
Data Enable—Data input registers are updated only when DE is
active.
Power down control—Application of ZZ will result in a low
standby power consumption.
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
Test Data Out
Test Clock
3.3 V power supply
Ground
2.5 V/3.3 V output power supply
No Connect
Rev: 1.05 7/2001
5/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Silicon Labs测评专区
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
