GS841Z18/36AT-180/166/150/100
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• 256K x 18 and 128K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
180 MHz–100 MHz
3.3 V V
DD
2.5 V and 3.3 V V
DDQ
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS841Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS841Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Functional Description
The GS841Z18/36AT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
t
KQ
tCycle
I
DD
–180
5.5 ns
3.2 ns
335 mA
8 ns
9.1 ns
210 mA
–166
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
–150
6.6 ns
3.8 ns
280 mA
10 ns
12 ns
165 mA
–100
10 ns
4.5 ns
190 mA
12 ns
15 ns
135 mA
Rev: 1.02 11/2004
1/30
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841Z18/36AT-180/166/150/100
GS841Z18T Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
V
DD
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
FT
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
NC
NC
A
8
A
9
A
17
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
QE
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
LBO
A
5
A
4
A
3
A
2
A
1
A
0
TMS
TDI
V
SS
V
DD
TDO
TCK
Rev: 1.02 11/2004
2/30
A
10
A
11
A
12
A
13
A
14
A
15
A
16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841Z18/36AT-180/166/150/100
GS841Z36T Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
V
DD
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
NC
NC
A
8
A
9
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
QE
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
LBO
A
5
A
4
A
3
A
2
A
1
A
0
TMS
TDI
V
SS
V
DD
TDO
TCK
A
10
A
11
Rev: 1.02 11/2004
3/30
A
12
A
13
A
14
A
15
A
16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841Z18/36AT-180/166/150/100
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A
DQ
B
DQ
C
DQ
D
ZZ
FT
LBO
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
In
In
In
—
—
—
—
In
In
In
Description
Burst Address Inputs—Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active high; for self decoded depth expansion
Chip Enable; active low; for self decoded depth expansion
Output Enable; active low
Advance / Load—Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
3.3 V power supply
Ground
3.3 V output power supply for noise reduction
Rev: 1.02 11/2004
4/30
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841Z18/36AT-180/166/150/100
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W
H
L
L
L
L
L
L
B
A
X
L
H
H
H
L
H
B
B
X
H
L
H
H
L
H
B
C
X
H
H
L
H
L
H
B
D
X
H
H
H
L
L
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.02 11/2004
5/30
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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