Product Preview
GS864018/32/36T-300/250/200/167
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
4M x 18, 2M x 32, 2M x 36
72Mb Sync Burst SRAMs
300 MHz–167 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS864018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS864018/32/36T is a 75,497,472-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-300
2.3
3.3
400
480
5.5
5.5
285
330
-250
2.5
4.0
340
410
6.5
6.5
245
280
-200
3.0
5.0
290
350
7.5
7.5
220
250
-167
3.5
6.0
260
305
8.0
8.0
210
240
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.00 9/2004
1/24
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview
GS864018/32/36T-300/250/200/167
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00 9/2004
5/24
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
