or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1010_01.4
Lattice Semiconductor
ispClock5300S Family Data Sheet
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-
chip in non-volatile E
2
CMOS
®
memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
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