LVDS, 1:4 Clock Buffer Terabuffer™
5T9304I
DATA SHEET
General Description
The 5T9304I differential clock buffer is a user-selectable differential
input to four LVDS outputs. The fanout from a differential input to four
LVDS outputs reduces loading on the preceding driver and provides
an efficient clock distribution network. The 5T9304I can act as a
translator from a differential HSTL, eHSTL, LVEPECL (2.5V),
LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A
single-ended 3.3V / 2.5V LVTTL input can also be used to translate
to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a
secondary clock source. Selectable reference inputs are controlled
by SEL.
The 5T9304I outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL
pin. Multiple power and grounds reduce noise.
Features
•
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•
•
•
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•
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Guaranteed low skew: 50ps (maximum)
Very low duty cycle distortion: 125ps (maximum)
Propagation delay: 1.9ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),
LVPECL (3.3V), CML or LVDS input interface
Selectable differential inputs to four LVDS outputs
2.5V V
DD
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Applications
•
Clock distribution
Pin Assignment
GND
PD
RESERVED
V
DD
Q1
Q1
Q2
Q2
V
DD
SEL
G
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A2
A2
GND
V
DD
Q3
Q3
Q4
Q4
V
DD
GL
A1
A1
5T9304I
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
G Package
Top View
5T9304I Rev A 5/13/15
1
©2015 Integrated Device Technology, Inc.
5T9304I DATA SHEET
Block Diagram
GL
G
OUTPUT
CONTROL
Q1
Q1
PD
OUTPUT
CONTROL
Q2
Q2
A1
A1
1
OUTPUT
CONTROL
Q3
Q3
A2
A2
0
OUTPUT
CONTROL
Q4
Q4
SEL
LVDS, 1:4 CLOCK BUFFER TERABUFFER™
2
Rev A 5/13/15
5T9304I DATA SHEET
Table 1. Pin Descriptions
Number
1, 12, 22
2
3
4, 9, 16, 21
5, 7,
18, 20
6, 8,
17, 19
10
Name
GND
PD
RESERVED
V
DD
Q1, Q2,
Q4, Q3
Q1, Q2,
Q4, Q3
SEL
Output
Output
Input
Input
Reserved
Power
LVDS
LVDS
LVTTL
Type
Power
LVTTL
Description
Power supply return for all power.
Power-down control. Shuts off entire chip. If LOW, the device goes into low
power mode. Inputs and outputs are disabled. Both Qx and Qx outputs will
pull to V
DD
. Set HIGH for normal operation.
(3)
Reserved pin.
Power supply for the device core and inputs.
Complementary differential clock outputs.
Differential clock outputs.
Reference clock select. When LOW, selects A2 and A2. When HIGH,
selects A1 and A1.
Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G
is LOW, the differential outputs are active. When G is HIGH, the differential
outputs are asynchronously driven to the level designated by GL
(2)
.
Clock input. A
[1:2]
is the "true" side of the differential clock input.
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]
.
For LVTTL single-ended operation, A[1:2] should be set to the desired
toggle voltage for A[1:2]:
3.3V LVTTL V
REF
= 1650mV
2.5V LVTTL V
REF
= 1250mV
Specifies output disable level. If HIGH, Qx outputs disable HIGH and Qx
outputs disable LOW. If LOW, Qx outputs disable LOW and Qx outputs
disable HIGH.
11
13, 24
G
A1, A2
Input
Input
LVTTL
Adjustable
(1, 4)
14, 23
A1, A2
Input
Adjustable
(1, 4)
15
GL
Input
LVTTL
NOTES:
1.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
4.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
3
Maximum
Units
pF
NOTE: This parameter is measured at characterization but not tested.
LVDS, 1:4 CLOCK BUFFER TERABUFFER™
3
Rev A 5/13/15
5T9304I DATA SHEET
Function Tables
Table 3A. Gate Control Output Table
Control Output
GL
0
0
1
1
G
0
1
0
1
Q[1:4]
Toggling
LOW
Toggling
HIGH
Outputs
Q[1:4]
Toggling
HIGH
Toggling
LOW
Table 3B. Input Selection Table
Selection SEL pin
0
1
Inputs
A2, A2
A1, A1
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Power Supply Voltage, V
DD
Input Voltage, V
I
Output Voltage, V
O
Not to exceed 3.6V
Storage Temperature, T
STG
Junction Temperature, T
J
Rating
-0.5V to + 3.6V
-0.5V to + 3.6V
-0.5 to V
DD
+ 0.5V
-65C to 150C
150C
Recommended Operating Range
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Minimum
-40
2.3
Typical
25
2.5
Maximum
85
2.7
Units
C
V
Rev A 5/13/15
4
LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5T9304I DATA SHEET
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics
(1)
,
V
DD
= 2.5V±0.2V, T
A
= -40°C to 85°C
Symbol
I
DDQ
I
TOT
I
PD
Parameter
Quiescent V
DD
Power Supply Current
Total Power V
DD
Supply Current
Total Power Down Supply Current
Test Conditions
V
DD
= Max.,
All Input Clocks = LOW
(2)
;
Output enabled
V
DD
= 2.7V;
F
REFERENCE
Clock = 450MHz
PD = LOW
Minimum
Typical
(2)
Maximum
240
Units
mA
250
5
mA
mA
NOTE 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2. The true input is held LOW and the complementary input is held HIGH.
Table 4B. LVCMOS/LVTTL DC Characteristics
(1)
,
V
DD
= 2.5V±0.2V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
IK
V
IN
V
IH
V
IL
V
THI
V
REF
Parameter
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Input High Voltage
DC Input Low Voltage
DC Input Threshold Crossing Voltage
Single-Ended Reference Voltage
(3)
3.3V LVTTL
2.5V LVTTL
V
DD
/2
1.65
1.25
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
-0.3
1.7
0.7
-0.7
Minimum
Typical
(2)
Maximum
±5
±5
-1.2
3.6
Units
µA
µA
V
V
V
V
V
V
V
NOTE 1. See
Recommended Operating Range
table.
NOTE 2. Typical values are at V
DD
= 2.5V, +25°C ambient.
NOTE 3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
Table 4C. Differential DC Characteristics
(1)
,
V
DD
= 2.5V±0.2V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
IK
V
IN
V
DIF
V
CM
Parameter
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage
(3)
DC Common Mode Input Voltage
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
-0.3
0.1
0.05
V
DD
-0.7
Minimum
Typical
(2)
Maximum
±5
±5
-1.2
3.6
Units
µA
µA
V
V
V
V
NOTE 1. See
Recommended Operating Range
table.
NOTE 2. Typical values are at V
DD
= 2.5V, +25°C ambient.
NOTE 3. V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
NOTE 4. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2.
LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5
Rev A 5/13/15
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