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74LV32AT14-13

产品描述Logic Gates Quad 2-Input 2, 5.5V OR Gates 12mA 4.5V
产品类别逻辑    逻辑   
文件大小309KB,共9页
制造商Diodes Incorporated
标准
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74LV32AT14-13概述

Logic Gates Quad 2-Input 2, 5.5V OR Gates 12mA 4.5V

74LV32AT14-13规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Diodes Incorporated
零件包装代码TSSOP
包装说明TSSOP,
针数14
Reach Compliance Codecompliant
Factory Lead Time17 weeks
系列LV/LV-A/LVX/H
JESD-30 代码R-PDSO-G14
JESD-609代码e3
长度5 mm
逻辑集成电路类型OR GATE
湿度敏感等级1
功能数量4
输入次数2
端子数量14
最高工作温度125 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd)20 ns
座面最大高度1.2 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级AUTOMOTIVE
端子面层Matte Tin (Sn)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
宽度4.4 mm
Base Number Matches1

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下载PDF文档
74LV32A
QUADRUPLE 2-INPUT OR GATES
Description
The 74LV32A provides provides four independent 2-input OR gates
with standard push-pull outputs. The device is designed for operation
with a power supply range of 2.0V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using I
OFF
. The I
OFF
circuitry disables the
output preventing damaging current backflow when the device is
powered down.
The gates perform the Boolean function:
Pin Assignments
Preliminary
NEW PRODUCT
Y
½
A
B
or
Y
½
A
B
Features
Wide Supply Voltage Range from 2.0V to 5.5V
Sinks or sources 12mA at V
CC
= 4.5V
CMOS low power consumption
I
OFF
Supports Partial -Power Down Operation
Inputs or Outputs accept up to 5.5V
Inputs can be driven by 3.3V or 5V allowing for voltage
translation applications.
Schmitt Trigger Action at All Inputs
ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Applications
General Purpose Logic
Power Down Signal Isolation
Wide array of products such as:
PCs, networking, notebooks, ultrabooks, netbooks
Computer peripherals, hard drives, CD/DVD ROM
TV, DVD, DVR, set top box
Latch-Up Exceeds 100mA per JESD 78, Class I
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
"Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl)
and <1000ppm antimony compounds.
Click for Ordering Information
74LV32A
Document number: DS35664 Rev. 1 - 2
1 of 9
www.diodes.com
October 2013
© Diodes Incorporated

74LV32AT14-13相似产品对比

74LV32AT14-13 74LV32AS14-13
描述 Logic Gates Quad 2-Input 2, 5.5V OR Gates 12mA 4.5V Logic Gates 6 Hex INV 2 to 5.5V Schmitt Trigger 12mA
是否Rohs认证 符合 符合
零件包装代码 TSSOP SOIC
包装说明 TSSOP, SOP,
针数 14 14
Reach Compliance Code compliant compliant
Factory Lead Time 17 weeks 17 weeks
系列 LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 代码 R-PDSO-G14 R-PDSO-G14
JESD-609代码 e3 e3
长度 5 mm 8.635 mm
逻辑集成电路类型 OR GATE OR GATE
湿度敏感等级 1 1
功能数量 4 4
输入次数 2 2
端子数量 14 14
最高工作温度 125 °C 125 °C
最低工作温度 -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP SOP
封装形状 RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
传播延迟(tpd) 20 ns 20 ns
座面最大高度 1.2 mm 1.73 mm
最大供电电压 (Vsup) 5.5 V 5.5 V
最小供电电压 (Vsup) 2 V 2 V
标称供电电压 (Vsup) 3.3 V 3.3 V
表面贴装 YES YES
技术 CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE
端子面层 Matte Tin (Sn) Matte Tin (Sn)
端子形式 GULL WING GULL WING
端子节距 0.65 mm 1.27 mm
端子位置 DUAL DUAL
宽度 4.4 mm 3.9 mm
Base Number Matches 1 1

 
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