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ispLSI 5256VA-70LB272: 产品描述CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD; 产品类别半导体可编程逻辑器件; 文件大小263KB，共28页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com

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ispLSI 5256VA-70LB272概述

CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD

ispLSI 5256VA-70LB272规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	Lattice(莱迪斯)
产品种类 Product Category	CPLD - Complex Programmable Logic Devices
RoHS	N
产品 Product	ispLSI 5256VA
Number of Macrocells	256
Number of Logic Array Blocks - LABs	8
Maximum Operating Frequency	70 MHz
Propagation Delay - Max	7.5 ns
Number of I/Os	44 I/O
工作电源电压 Operating Supply Voltage	3.3 V
最小工作温度 Minimum Operating Temperature	0 C
最大工作温度 Maximum Operating Temperature	+ 70 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	BGA-272
系列 Packaging	Tray
高度 Height	1.6 mm
长度 Length	27 mm
Memory Type	EEPROM
宽度 Width	27 mm
Number of Gates	12000
Moisture Sensitive	Yes
工厂包装数量 Factory Pack Quantity	40
电源电压-最大 Supply Voltage - Max	3.6 V
电源电压-最小 Supply Voltage - Min	3 V
单位重量 Unit Weight	0.110817 oz

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ispLSI 5256VA

In-System Programmable

3.3V SuperWIDE™ High Density PLD

Features

• SuperWIDE HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 12000 PLD Gates / 256 Macrocells

— Up to 192 I/O Pins

— 256 Registers

— High-Speed Global Interconnect

— SuperWIDE 32 Generic Logic Block (GLB) Size for

Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package Options

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 125 MHz Maximum Operating Frequency

—

= 7.5 ns Propagation Delay

— Enhanced

su2

= 7 ns,

su3 (CLK0/1)

= 4.5ns,

su3 (CLK2/3)

= 3.5ns

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Slew and Skew Programmable I/O (SASPI/O)

Supports Programmable Bus Hold, Pull-up, Open

Drain and Slew and Skew Rate Options

— Six Global Output Enable Terms, Two Global OE

Pins and One Product Term OE per Macrocell

— PC and UNIX Platforms

Functional Block Diagram

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Boundary

Scan

Interface

Generic

Logic Block

Generic

Logic Block

Input Bus

Global Routing Pool

(GRP)

Generic

Logic Block

Generic

Logic Block

Input Bus

Generic

Logic Block

Generic

Logic Block

Input Bus

ispLSI 5000V Description

The ispLSI 5000V Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and five extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be by-

passed for functions of five product terms or less. The

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

5256va_06

ispLSI 5256VA-70LB272相似产品对比

	ispLSI 5256VA-70LB272	ispLSI-5256VA-70LB272I	ispLSI-5256VA-100LB272	ispLSI-5256VA-70LB208	ispLSI 5256VA-100LQ208	ispLSI 5256VA-125LB208	ispLSI 5256VA-125LQ208	ispLSI 5256VA-70LQ208
描述	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD	CPLD - Complex Programmable Logic Devices PROGRAM SUPERWIDE HI DENSITY PLD
Product Attribute	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value
制造商 Manufacturer	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)
产品种类 Product Category	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices	CPLD - Complex Programmable Logic Devices
RoHS	N	N	N	N	N	N	N	N
产品 Product	ispLSI 5256VA	ispLSI 5256VA	ispLSI 5256VA	ispLSI 5256VA	ispLSI 5256VA	ispLSI 5256VA	ispLSI 5256VA	ispLSI 5256VA
Number of Macrocells	256	256	256	256	256	256	256	256
Number of Logic Array Blocks - LABs	8	8	8	8	8	8	8	8
Maximum Operating Frequency	70 MHz	70 MHz	100 MHz	70 MHz	100 MHz	125 MHz	125 MHz	70 MHz
Propagation Delay - Max	7.5 ns	7.5 ns	7.5 ns	7.5 ns	7.5 ns	7.5 ns	7.5 ns	7.5 ns
Number of I/Os	44 I/O	44 I/O	32 I/O	44 I/O	32 I/O	32 I/O	40 I/O	44 I/O
工作电源电压 Operating Supply Voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
最小工作温度 Minimum Operating Temperature	0 C	- 40 C	0 C	0 C	0 C	0 C	0 C	0 C
最大工作温度 Maximum Operating Temperature	+ 70 C	+ 105 C	+ 70 C	+ 70 C	+ 70 C	+ 70 C	+ 70 C	+ 70 C
安装风格 Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
封装 / 箱体 Package / Case	BGA-272	BGA-272	BGA-272	PQFP-208	PQFP-208	FPBGA-208-32	BGA-272	FPBGA-256-44
系列 Packaging	Tray	Tray	Tray	Tray	Tray	Tray	Tray	Tray
高度 Height	1.6 mm	1.6 mm	1.6 mm	1.2 mm	3.4 mm	1.2 mm	3.4 mm	3.4 mm
长度 Length	27 mm	27 mm	27 mm	17 mm	28 mm	17 mm	28 mm	28 mm
Memory Type	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM
宽度 Width	27 mm	27 mm	27 mm	17 mm	28 mm	17 mm	28 mm	28 mm
Number of Gates	12000	12000	12000	12000	12000	12000	12000	12000
Moisture Sensitive	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
工厂包装数量 Factory Pack Quantity	40	40	40	90	24	90	24	24
电源电压-最大 Supply Voltage - Max	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
电源电压-最小 Supply Voltage - Min	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V

ispLSI 5256VA-70LB272

ispLSI 5256VA-70LB272概述

ispLSI 5256VA-70LB272规格参数

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