NXP Semiconductors
Data sheet: Technical Data
Document Number: MC34937
Rev. 3.0, 5/2016
Three phase field effect transistor
pre-driver
The 34937A is a field effect transistor (FET) pre-driver designed for three phase
motor control and similar applications. The integrated circuit (IC) uses
SMARTMOS technology.
The IC contains three high-side FET pre-drivers and three low-side FET pre-
drivers. Three external bootstrap capacitors provide gate charge to the high-
side FETs.
The IC interfaces to a MCU via six direct input control signals, an SPI port for
device setup and asynchronous reset, enable, and interrupt signals. Both 5.0 V
and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are
provided.
Features
•
•
•
•
•
•
•
•
•
•
•
Extended supply voltage operating range: 6.0 V to 58 V
Gate drive capability of 1.0 A to 2.5 A
Wide deadtime range (50 ns to 12
μs)
programmable via the SPI port
Charge pump ensures sufficient external FET drive at low supply voltages
Device protection against reverse charge-injection from C
GD
and C
GS
of
external FETS
Integrated overcurrent, desaturation, and phase fault-detection
Immunity against positive or negative transient voltage spikes on the gate
driver
Current shoot-through protection built into deadtime control
Supports direct 3.3 V and 5.0 V logic interface to MCUs
Integrated current sensing amplifier
Device configuration and diagnostics through the SPI
34937A
Industrial
THREE PHASE PRE-DRIVER
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
Applications
• 12 V to 48 V 3-phase brushless DC (BLDC) motors
and permanent magnet synchronous motors (PMSM)
• E-Bike, hospital beds, electric scooters
• CPAPs, inflation pumps, industrial fans
• Portable power tools, commercial fans/blowers
• Small kitchen appliances
V
SYS
VPUMP
PUMP
VPWR
VLS
VDD
VSS
3
3
3
34937
VSUP
PA_HS_G
PB_HS_G
PC_HS_G
PA_HS_S
PB_HS_S
PC_HS_S
MCU
OR
DSP
PX_HS
PX_LS
PHASEX
CS
SI
SCLK
SO
RST
INT
EN1
EN2
GND
PA_LS_G
PB_LS_G
PC_LS_G
PX_LS_S
AMP_P
AMP_N
AMP_OUT
R
SEN
Figure 1. 34937A simplified application diagram
© 2016 NXP B.V.
1
Orderable parts
Table 1. Orderable part variations
Part number
(1)
MC34937APEK
Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
Notes
Temperature (T
A
)
-40 °C to 125 °C
Package
54 SOICW-EP
34937A
2
NXP Semiconductors
2
Internal block diagram
PUMP
VPWR
VSUP
VPUMP
PGND
MAIN
CHARGE
PUMP
TRICKLE
CHARGE
PUMP
5.0 V
REG.
VDD
OSCILLATOR
UV
DETECT
3X
HOLD
-OFF
CIRCUIT
VLS
REG.
VLS
VDD
RST
INT
EN1
EN2
PX_HS
PX_LS
CS
SI
SCLK
SO
PHASEX
OC_OUT
GND(2)
+
-
OVERCUR.
COMP.
3
3
3
T-LIM
VSUP
+
DESAT. 1.4 V
-
COMP
+
-
HIGH
-SIDE
DRIVER
PX_BOOT
PX_HS_G
CONTROL
LOGIC
PX_HS_S
+
-
PHASE
VSUP
COMP.
LOW
SIDE
DRIVER
PX_LS_G
+
-
I-SENSE
AMP.
AMP_N
AMP_P
VLS_CAP
PX_LS_S
VSS OC_TH AMP_OUT
Figure 2. 34937A simplified internal block diagram
34937A
NXP Semiconductors
3
3
3.1
Pin Connections
Pinout diagram
Transparent
Top View
PHASEA
PGND
EN1
EN2
RST
N/C
PUMP
VPUMP
VSUP
PHASEB
PHASEC
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
.35
34
33
32
31
30
29
28
VPWR
N/C
N/C
VLS
N/C
N/C
PA_BOOT
PA_HS_G
PA_HS_S
PA_LS_G
PA_LS_S
PB_BOOT
PB_HS_G
PB_HS_S
PB_LS_G
PB_LS_S
PC_BOOT
PC_HS_G
PC_HS_S
PC_LS_G
PC_LS_S
N/C
VLS_CAP
GND1
GND0
VSS
OC_TH
Figure 3. 34937A pin connections
3.2
Pin definitions
A functional description of each pin can be found in the
Functional pin description
section beginning on
page 20.
Table 2. 34937A pin definitions
Pin
1
2
3
4
5
6, 33, 49,
50, 52, 53
7
8
9
Pin name
PHASEA
PGND
EN1
EN2
RST
N/C
PUMP
VPUMP
VSUP
Pin function
Digital output
Ground
Digital input
Digital input
Digital input
–
Power drive
out
Power input
Analog input
Formal name
Phase A
Power ground
Enable 1
Enable 2
Reset
No Connect
Pump
Voltage pump
Supply voltage
Definition
Totem pole output of Phase A comparator. This output is low when the voltage on
PA_HS_S (source of high-side FET) is less than 50% of V
SUP
Power ground for charge pump
Logic signal input must be high (ANDed with EN2) to enable any gate drive output.
Logic signal input must be high (ANDed with EN1) to enable any gate drive output
Reset input
Do not connect these pins
Charge pump output
Charge pump supply
Supply voltage to the load. This pin is to be connected to the common drains of the
external high-side FETs
34937A
4
NXP Semiconductors
Table 2. 34937A pin definitions (continued)
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30, 31
32
34
35
36
37
38
39
40
41
42
43
44
45
Pin name
PHASEB
PHASEC
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
OC_TH
VSS
GND
VLS_CAP
PC_LS_S
PC_LS_G
PC_HS_S
PC_HS_G
PC_BOOT
PB_LS_S
PB_LS_G
PB_HS_S
PB_HS_G
PB_BOOT
PA_LS_S
PA_LS_G
Pin function
Digital output
Digital output
Digital input
Digital input
Analog output
Digital input
Digital input
Digital output
Digital input
Digital input
Digital input
Digital output
Digital input
Digital input
Analog output
Analog input
Analog input
Digital output
Analog input
Ground
Ground
Analog output
Power input
Power output
Power input
Power output
Analog input
Power input
Power output
Power input
Power output
Analog input
Power input
Power output
Formal name
Phase B
Phase C
Phase A high-side
Phase A low-side
VDD Regulator
Phase B high-side
Phase B low-side
Interrupt
Chip select
Serial in
Serial clock
Serial out
Phase C low-side
Phase C high-side
Amplifier output
Amplifier invert
Amplifier non-Invert
Overcurrent out
Overcurrent threshold
Definition
Totem pole output of Phase B comparator. This output is low when the voltage on
PB_HS_S (source of high-side FET) is less than 50% of V
SUP
Totem pole output of Phase C comparator. This output is low when the voltage on
PC_HS_S (source of high-side FET) is less than 50% of V
SUP
Active low input logic signal enables the high-side driver for Phase A
Active high input logic signal enables the low-side driver for Phase A
VDD regulator output capacitor connection.
Active low input logic signal enables the high-side driver for Phase B
Active high input logic signal enables the low-side driver for Phase B
Interrupt pin output
Chip select input. It frames SPI commands and enables SPI port
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Clock for SPI port and typically is 3.0 MHz
Output data for SPI port. Tri-state until CS becomes low
Active high input logic signal enables the low-side driver for Phase C
Active low input logic signal enables the high-side driver for Phase C
Output of the current-sensing amplifier
Inverting input of the current-sensing amplifier
Non-inverting input of the current-sensing amplifier
Totem pole digital output of the overcurrent comparator
Threshold of the overcurrent detector
Voltage source supply Ground reference for logic interface and power supplies
Ground
VLS regulator output
capacitor
Phase C low-side
source
Substrate and ESD reference, connect to VSS
VLS regulator connection for additional output capacitor, providing low-impedance
supply source for low-side gate drive
Source connection for Phase C low-side FET
Phase C low-side gate
Gate drive output for Phase C low-side
drive
Phase C high-side
source
Source connection for Phase C high-side FET
Phase C high-side gate
Gate drive for output Phase C high-side FET
drive
Phase C bootstrap
Phase B low-side
source
Bootstrap capacitor for Phase C
Source connection for Phase B low-side FET
Phase B low-side gate
Gate drive for output Phase B low-side
drive
Phase B high-side
source
Source connection for Phase B high-side FET
Phase B high-side gate
Gate drive for output Phase B high-side
drive
Phase B bootstrap
Phase A low-side
source
Bootstrap capacitor for Phase B
Source connection for Phase A low-side FET
Phase A low-side gate
Gate drive for output Phase A low-side
drive
34937A
NXP Semiconductors
5
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