32 Mbit Concurrent SuperFlash + 16 Mbit
PSRAM ComboMemory
GLS34HF32A4
GLS34HF32x4x32Mb CSF + 4/8/16 Mb SRAM (x16) MCP ComboMemory
Preliminary Specifications
FEATURES:
• Flash Organization: 2M x16 or 4M x8
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– 32 Mbit Top Sector Protection
– 32 Mbit: 8 Mbit + 24Mbit
• PSRAM Organization:
– 16 Mbit: 1024K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 70 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 8 KWord in the smaller bank by holding
WP# low and unprotects by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Byte Selection for Flash (CIOF pin)
– Selects 8-bit or 16-bit mode (56-ball package
only)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Flash Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
• Erase-Suspend / Erase-Resume Capabilities
• Read Access Time
– Flash: 70 ns
– PSRAM: 70 ns
• Security ID Feature
– Greenliant: 128 bits
– User: 256 Bytes
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Word-Program Time: 7 µs
• Automatic Write Timing
– Internal
V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Packages Available
– 56-ball LFBGA (8mm x 10mm)
– 62-ball LFBGA (8mm x 10mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The GLS34HF32A4 ComboMemory integrates either a 2M
x16 or 4M x8 CMOS flash memory bank with 1024K x16
CMOS pseudo SRAM (PSRAM) memory bank in a multi-
chip package (MCP). This device is fabricated using
Greenliant proprietary, high-performance CMOS Super-
Flash technology incorporating the split-gate cell design
and thick-oxide tunneling injector to attain better reliability
and
manufacturability
compared
with
alternate
approaches. The GLS34HF32A4 is ideal for applications
such as cellular phones, GPS devices, PDAs, and other
portable electronic devices in a low power and small form
factor system.
The GLS34HF32A4 features dual flash memory bank
architecture allowing for concurrent operations between
the two flash memory banks and the PSRAM. The device
can read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 8 Mbit and 24 Mbit with
top sector protection options for storing boot code, program
code, configuration/parameter data and user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The GLS34HF32A4 offers a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
operations, the flash memory banks provide a typical
©2010 Greenliant Systems, Ltd.
www.greenliant.com
S71313-06-000
05/10
32 Mbit Concurrent SuperFlash + 16 Mbit PSRAM
ComboMemory GLS34HF32A4
Preliminary Specifications
Word-Program time of 7 µsec. To protect against inadver-
tent flash write, the GLS34HF32A4 contains on-chip hard-
ware and software data protection schemes.
The flash and PSRAM operate as two independent mem-
ory banks with respective bank enable signals. The mem-
ory bank selection is done by two bank enable signals. The
PSRAM bank enable signals, BES1# and BES2, select the
PSRAM bank. The flash memory bank enable signal,
BEF#, has to be used with Software Data Protection (SDP)
command sequence when controlling the Erase and Pro-
gram operations in the flash memory bank. The memory
banks are superimposed in the same memory address
space where they share common address lines, data lines,
WE# and OE# which minimize power consumption and
area.
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the GLS34HF32A4 is
offered in both commercial and extended temperatures and
a small footprint package to meet board space constraint
requirements. See Figure 3 for pin assignments.
Concurrent Read/Write Operation
Dual bank architecture of GLS34HF32A4 devices allows
the Concurrent Read/Write operation whereby the user
can read from one bank while programming or erasing in
the other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank. See Table 3 for dual-bank memory
organization.
Concurrent Read/Write States
Flash
Bank 1
Read
Write
Write
No Operation
Write
No Operation
Bank 2
Write
Read
No Operation
Write
No Operation
Write
PSRAM
No Operation
No Operation
Read
Read
Write
Write
Device Operation
The GLS34HF32A4 uses BES1#, BES2 and BEF# to con-
trol operation of either the flash or the PSRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the PSRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time.
If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
PSRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to V
IHC
(Logic High) or
when BEF# is high and BES2 is low.
Note:
For the purposes of this table, write means to perform
Block-/Sector-Erase or Program operations
as applicable to the appropriate bank.
Flash Read Operation
The Read operation of the GLS34HF32A4 is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram in Figure 8 for
details.
©2010 Greenliant Systems, Ltd.
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32 Mbit Concurrent SuperFlash + 16 Mbit PSRAM
ComboMemory GLS34HF32A4
Preliminary Specifications
Flash Program Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the CIOF pin.
Before programming, one must ensure that the sector
being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or BEF#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Figures 9 and 10 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 23 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
Flash Chip-Erase Operation
The GLS34HF32A4 provide a Chip-Erase operation, which
allows the user to erase all flash sectors/blocks to the “1”
state. This is useful when the device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or BEF#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bits or Data# Poll-
ing. See Table 6 for the command sequence, Figure 13 for
timing diagram, and Figure 27 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored.
Flash Erase-Suspend/-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within erase-suspended sectors/blocks will output DQ
2
tog-
gling and DQ
6
at “1”. While in Erase-Suspend mode, a Pro-
gram operation is allowed except for the sector or block
selected for Erase-Suspend. To resume Sector-Erase or
Block-Erase operation which has been suspended, the
system must issue an Erase-Resume command. The
operation is executed by issuing a one-byte command
sequence with Erase Resume command (30H) at any
address in the one-byte sequence.
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector-Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector-Erase command (50H) and sector address (SA) in
the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase
command (30H) and block address (BA) in the last bus
cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse.
The internal Erase operation begins after the sixth WE#
pulse. Any commands issued during the Block- or Sector-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 14 and 15 for timing wave-
forms.
©2010 Greenliant Systems, Ltd.
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32 Mbit Concurrent SuperFlash + 16 Mbit PSRAM
ComboMemory GLS34HF32A4
Preliminary Specifications
Flash Write Operation Status Detection
The GLS34HF32A4 provide one hardware and two soft-
ware means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write
cycle time. The hardware detection uses the Ready/
Busy# (RY/BY#) pin. The software detection includes
two status bits: Data# Polling (DQ
7
) and Toggle Bit
(DQ
6
). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Pro-
gram or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy#
(RY/BY#), Data# Polling (DQ
7
) or Toggle Bit (DQ
6
) read
may be simultaneous with the completion of the Write
cycle. If this occurs, the system may possibly get an erro-
neous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious rejection, if
an erroneous result occurs, the software routine should
include a loop to read the accessed location an additional
two (2) times. If both reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
Byte/Word (CIOF)
This function, found only on the 56-ball package, includes a
CIOF pin to control whether the device data I/O pins oper-
ate x8 or x16. If the CIOF pin is at logic “1” (V
IH
) the device
is in x16 data configuration: all data I/0 pins DQ
0
-DQ
15
are
active and controlled by BEF# and OE#.
If the CIOF pin is at logic “0”, the device is in x8 data config-
uration: only data I/O pins DQ
0
-DQ
7
are active and con-
trolled by BEF# and OE#. The remaining data pins DQ
8
-
DQ
14
are at Hi-Z, while pin DQ
15
is used as the address
input A
-1
for the Least Significant Bit of the address bus.
Flash Data# Polling (DQ
7
)
When the devices are in an internal Program operation,
any attempt to read DQ
7
will produce the complement of
the true data. Once the Program operation is completed,
DQ
7
will produce true data. During internal Erase operation,
any attempt to read DQ
7
will produce a ‘0’. Once the inter-
nal Erase operation is completed, DQ
7
will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth
WE# (or BEF#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or BEF#) pulse. See Figure 11 for
Data# Polling (DQ
7
) timing diagram and Figure 24 for a
flowchart.
Ready/Busy# (RY/BY#)
The GLS34HF32A4 include a Ready/Busy# (RY/BY#) out-
put signal. RY/BY# is an open drain output pin that indi-
cates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to V
DD
via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
©2010 Greenliant Systems, Ltd.
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32 Mbit Concurrent SuperFlash + 16 Mbit PSRAM
ComboMemory GLS34HF32A4
Preliminary Specifications
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ
6
will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
6
will
toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table
1 shows detailed status bit information. The Toggle Bit
(DQ
2
) is valid after the rising edge of the last WE# (or
BEF#) pulse of a Write operation. See Figure 12 for Toggle
Bit timing diagram and Figure 24 for a flowchart.
TABLE 1: Write Operation Status
Status
Normal
Standard
Operation Program
Standard
Erase
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
DQ
7
DQ7#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
RY/BY#
0
0
1
Data Protection
The GLS34HF32A4 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadver-
tent writes during power-up or power-down.
Hardware Block Protection
The GLS34HF32A4 provide a hardware block protection
which protects the outermost 8 KWord in Bank 1. The
block is protected when WP# is held low.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate
and return to Read mode (see Figure 20). When no inter-
nal Program/Erase operation is in progress, a minimum
period of T
RHR
is required after RST# is driven high before
a valid Read can take place (see Figure 19).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 19 and 20 for timing
diagrams.
Data
Data
Data
1
DQ7#
Toggle
No Toggle
0
T1.1 1313
Note:
DQ
7,
DQ
6,
and DQ
2
require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
©2010 Greenliant Systems, Ltd.
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S71313-06-000
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