TECHNICAL DATA
IN74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
) inputs;
also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action in
the clock input makes the circuit highly tolerant to slower clock rise and
fall times.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Supply voltage range: 1.2 to 3.6 V
•
Low input current: 1.0
µÀ;
0.1
µÀ
at Ò = 25
°Ñ
•
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC
14
1
14
D SUFFIX
SOIC
1
ORDERING INFORMATION
IN74LV74N
IN74LV74D
IZ74LV74
Plastic DIP
SOIC
chip
T
A
= -40° to 125° C for all packages
PIN ASSIGNMENT
RESET 1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
RESET 2
DATA2
CLOCK 2
SET 2
Q2
Q2
LOGIC DIAGRAM
DATA 1
CLOCK 1
SET 1
Q1
Q1
GND
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
PIN 20=V
CC
PIN 10 = GND
H
H
Reset
H
L
L
H
H
H
H
H
L
H
Clock
X
X
X
Data
X
X
X
H
L
X
X
X
Outputs
Q
H
L
H*
H
L
Q
L
H
H*
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level
L = low level
X = don’t care
Z = high impedance
INTEGRAL
1
IN74LV74
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
DC supply voltage
Input diode current
Output diode current
Output source or sink current
V
CC
current
GND current
Power dissipation per package:
Plastic DIP *
4
SO *
4
Storage Temperature
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
Parameter
Value
-0.5 to +5.0
±20
±50
±35
±70
±70
750
500
-65 to +150
260
°C
°C
Unit
V
mA
mA
mA
mA
mA
mW
Tstg
T
L
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: - 8 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time except for Schmitt-
trigger inputs (Figure 1)
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
Parameter
Min
1.2
0
0
-40
0
0
0
0
Max
3.6
V
CC
V
CC
+125
1000
700
500
400
Unit
V
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must b e left open.
INTEGRAL
2
IN74LV74
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
Symbol
Parameter
conditions
V
CC
V
25°C
min
V
IH
HIGH level input
voltage
1.2
2.0
3.0
3.6
1.2
2.0
3.0
3.6
V
I
= V
IH
or V
IL
I
O
= -50
µÀ
1.2
2.0
3.0
3.6
3.0
1.2
2.0
3.0
3.6
3.0
*
*
0.9
1.4
2.1
2.5
-
-
-
-
1.1
1.92
2.92
3.52
2.48
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.09
0.09
0.09
0.09
0.33
±0.1
4.0
Guaranteed Limit
-40°C to 85°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
2.34
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.1
0.1
0.1
0.1
0.4
±1.0
40
125°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
2.20
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.1
0.1
0.1
0.1
0.5
±1.0
80
V
Unit
V
IL
LOW level output
voltage
V
V
OH
HIGH level output
voltage
V
V
I
= V
IH
or V
IL
I
O
= -6mÀ
V
OL
LOW level output
voltage
V
I
= V
IH
or V
IL
I
O
= 50
µÀ
V
V
V
I
= V
IH
or V
IL
I
O
= 6 mÀ
I
I
I
CC
Input current
Supply current
V
I
= V
CC
or 0 V
V
I
=V
CC
or 0 V
I
O
= 0
µÀ
V
µÀ
µÀ
* V
CC
= 3.3
±
0.3 V
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
Symbol
Parameter
conditions
V
CC
V
25°C
min
t
PHL,
t
PLH
Propagation delay , Clock
to Q or Q
t
PHL,
t
PLH
Propagation delay , Set to
Q or Q
t
PHL,
t
PLH
Propagation delay , Reset
to Q or Q
t
THL,
t
TLH
Output Transition Time,
Any Output
C
I
Input capacitance
V
I
= 0 V or V
CC
Figures 1,3
V
I
= 0 V or V
CC
Figures 2,3
V
I
= 0 V or V
CC
Figures 2,3
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
1.2
2.0
*
1.2
2.0
*
1.2
2.0
*
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
max
140
45
28
150
44
27
160
47
29
90
20
15
7.0
Guaranteed Limit
-40°C to
85°C
min
-
-
-
-
-
-
-
-
-
-
-
-
-
max
160
56
35
170
54
34
180
58
37
110
25
19
-
min
-
-
-
-
-
-
-
-
-
-
-
-
-
125°C
max
180
67
42
190
65
41
200
70
44
130
30
23
-
ns
Unit
ns
ns
ns
pF
INTEGRAL
3
IN74LV74
C
PD
Power dissipation
capacitance (per flip-flop)
V
I
= 0 V or V
CC
-
48
-
-
-
-
pF
INTEGRAL
4
IN74LV74
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
Symbol
Parameter
Puls e Width, Clock, Set or
Reset
Setup Time, Data to Clock
conditions
V
CC
V
25°C
min
t
w
V
I
= 0 V or V
CC
Figures 1,2,3
V
I
= 0 V or V
CC
Figures 1,3
V
I
= 0 V or V
CC
Figures 2,3
V
I
= 0 V or V
CC
Figures 1,3
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
1.2
2.0
*
1.2
2.0
*
1.2
2.0
*
1.2
2.0
3.0
75
25
16
25
16
10
18
9
6
3
3
3
8
18
30
max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Guaranteed Limit
-40°C to 85°C
min
96
32
20
32
20
13
24
12
8
5
3
3
6
15
24
max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125°C
min
114
38
24
40
24
15
30
15
9
5
3
3
4
12
20
max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Unit
t
su
ns
t
rem
Removal Time, Set or
Reset to Clock
Hold Time, Clock to Data
ns
t
h
ns
f
c
Clock Frequency
MHz
* V
CC
= 3.3
±
0.3 V
V
M
= 0.5
∗
V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 1. Switching Waveforms
INTEGRAL
5
嵌入式系统
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