TECHNICAL DATA
IN74LV241
OCTAL BUFFER/LINE DRIVE; 3-STATE
The IN74LV241 is a low-voltage Si-gate CMOS device and is pin and
function compatible with IN74HC/HCT241.
The IN74LV241 is an octal non-inverting buffer/line driver with 3-
state outputs. The 3-state outputs are controlled by the output enable
inputs 1OE and 2OE.
•
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 1.2 to 3.6 V
Low Input Current: 1.0
µA,
0.1
µÀ
at Ò = 25
°Ñ
Output Current: 8 mA at V
CC
= 3.0 V
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
IN74LV241N
IN74LV241DW
IZ74LV241
Plastic DIP
SOIC
chip
T
A
= -40° to 125° C for all packages
LOGIC DIAGRAM
1A
0
1A
1
1A
2
1A
3
DATA
INPUTS
2A
0
2A
1
2
18
PIN ASSIGNMENT
1Y
0
1Y
1
1Y
2
1Y
3
2Y
0
2Y
1
2Y
0
2Y
1
NONINVERTING
OUTPUTS
4
6
8
11
13
16
14
12
9
7
5
1OE
1A
0
2Y
3
1A
1
2Y
2
1A
2
2Y
1
1A
3
2Y
0
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2OE
1Y
0
2A
3
1Y
1
2A
2
1Y
2
2A
1
1Y
3
2A
0
2A
0
15
2A
1
17
3
OUTPUT
ENABLES
1OE
2OE
1
19
FUNCTION TABLE
Input
1OE
L
PIN 20=V
CC
PIN 10 = GND
L
H
1An
L
H
X
Output
1Yn
L
H
Z
Input
2OE
H
H
L
2An
L
H
X
Output
2Yn
L
H
Z
H= high level
L = low level
X = don’t care
Z = high impedance
INTEGRAL
1
IN74LV241
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
DC supply voltage
DC Input diode current
DC Output diode current
DC Output source or sink current
DC V
CC
current
DC GND current
Power dissipation per package: *
4
Plastic DIP
SO
Storage Temperature
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
Parameter
Value
-0.5 to +5.0
±20
±50
±35
±70
±70
750
500
-65 to +150
260
°C
°C
Unit
V
mA
mA
mA
mA
mA
mW
Tstg
T
L
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
t
r
, t
f
DC Supply Voltage
Input Voltage
Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
Parameter
Min
1.2
0
0
-40
0
0
0
0
Max
3.6
V
CC
V
CC
+125
1000
700
500
400
Unit
V
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
INTEGRAL
2
IN74LV241
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
Symbol
Parameter
conditions
V
CC
V
25°C
min
V
IH
HIGH level input
voltage
1.2
2.0
3.0
3.6
1.2
2.0
3.0
3.6
V
I
= V
IH
or V
IL
I
O
= -50
µÀ
1.2
2.0
3.0
3.6
3.0
1.2
2.0
3.0
3.6
3.0
*
1.2
*
*
0.9
1.4
2.1
2.5
-
-
-
-
1.1
1.92
2.92
3.52
2.48
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.09
0.09
0.09
0.09
0.33
±0.1
±0.5
Guaranteed Limit
-40°C to 85°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
2.34
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.1
0.1
0.1
0.1
0.4
±1.0
±5
125°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
2.20
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.1
0.1
0.1
0.1
0.5
±1.0
±10
V
Unit
V
IL
LOW level input
voltage
V
V
OH
HIGH level output
voltage
V
V
I
= V
IH
or V
IL
I
O
= -8 mÀ
V
OL
LOW level output
voltage
V
I
= V
IH
or V
IL
I
O
= 50
µÀ
V
V
V
I
= V
IH
or V
IL
I
O
= 8 mÀ
I
I
I
OZ
Input current
V
I
= V
CC
or 0 V
V
µÀ
µÀ
Three state leakage 3-state outputs
current
V
I
(01,19) = V
IH
V
O
=V
CC
or 0 V
Supply current
V
I
=V
CC
or 0 V
I
O
= 0
µÀ
I
CC
-
8.0
-
80
-
160
µÀ
* V
CC
= 3.3
±
0.3 V
INTEGRAL
3
IN74LV241
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
Symbol
Parameter
conditions
V
CC
V
25°C
min
t
PHL,
t
PLH
Propagation delay , 1An
to 1Yn, 2An to 2Yn
t
PHZ
t
PLZ
V
I
= 0 V or V
CC
Figure 1 and 3
1.2
2.0
*
1.2
2.0
*
1.2
2.0
*
1.2
2.0
*
3.0
V
I
= 0 V or V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
100
24
15
140
30
20
140
32
20
60
16
10
7.0
70
Guaranteed Limit
-40°C to
85°C
min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
125
30
19
175
35
24
175
40
25
75
20
13
7.0
-
125°C
min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
150
36
23
210
41
28
210
48
30
90
24
15
7.0
-
ns
Unit
Propagation delay, 1OE to V
I
= 0 V or V
CC
1Yn, 2OE to 2Yn
Figure 2 and 4
Propagation delay, 1OE to V
I
= 0 V or V
CC
1Yn, 2OE to 2Yn
Figure 2 and 4
V
I
= 0 V or V
CC
Figure 1 and 3
ns
t
PZH
t
PZL
ns
t
THL,
t
TLH
Output Transition Time,
Any Output
C
I
C
PD
Input capacitance
Power dissipation
capacitance (per one
channel)
ns
pF
pF
* V
CC
= 3.3
±
0.3 V
V
CC
tr
1A
n
or 2A
n
10%
90%
50%
tf
1OE
50%
V
CC
GND
t
PHL
2OE
t
PZL
1Y
n
or 2Y
n
GND
V
CC
50%
GND
t
PLZ
V
CC
50%
t
PLH
1Y
n
or 2Y
n
t
TLH
50%
10%
90%
t
THL
t
PZH
1Y
n
or 2Y
n
50%
)
t
PHZ
V
OL
V
OH
GND
Figure 1. Switching Waveforms
TEST POINT
Figure 2. Switching Waveforms
TEST POINT
1k
C
L
*
DEVICE
UNDER
TEST
OUTPUT
*
C
L
DEVICE
UNDER
TEST
OUTPUT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND when
testing t
PHZ
and t
PZH
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
INTEGRAL
4
IN74LV241
Figure 3. Test Circuit
Figure 4. Test Circuit
CHIP PAD DIAGRAM
Chip marking
25LV241
13
18
1.65+ 0.03
17
19
20
16
15
14
12
11
10
01
09
02
03
Y
(0,0)
X
Location of marking (mm):
left lower corner x=1.539, y=1.433.
Chip thickness:
0.46
±
0.02 mm.
PAD LOCATION
Pad No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
Symbol
1OE
1A
0
2Y
3
1A
1
2Y
2
2A
2
2Y
1
2A
3
2Y
0
GND
2A
0
1Y
3
2A
1
1Y
2
2A
2
1Y
1
2A
3
1Y
0
2OE
V
CC
Location (left lower corner), mm
X
0.115
0.1075
0.3215
0.76
0.9285
1.2115
1.4615
1.674
1.674
1.685
1.674
1.6795
1.674
1.0525
0.7545
0.586
0.293
0.112
0.112
0.112
Y
0.55
0.246
0.131
0.131
0.131
0.131
0.131
0.131
0.43
0.643
1.0855
1.266
1.4345
1.4345
1.4345
1.4345
1.4345
1.4345
1.1385
0.949
Pad size, mm
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
04 05
06
07
08
1.9 + 0.03
Note: Pad location is given as per metallization layer
INTEGRAL
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
