Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers
July 2006
Single-Channel: 6N138, 6N139
Dual-Channel: HCPL-2730, HCPL-2731
Low Input Current High Gain Split
Darlington Optocouplers
Features
Low current - 0.5 mA
Superior CTR-2000%
Superior CMR-10 kV/µs
CTR guaranteed 0-70°C
U.L. recognized (File # E90700)
VDE recognized (File # 120915) Ordering option
V, e.g., 6N138V
■
Dual Channel - HCPL-2730
■
HCPL-2731
■
■
■
■
■
■
tm
Description
The 6N138/9 and HCPL-2730/HCPL-2731 optocouplers consist
of an AlGaAs LED optically coupled to a high gain split darling-
ton photodetector.
The split darlington configuration separating the input photo-
diode and the first stage gain from the output transistor permits
lower output saturation voltage and higher speed operation than
possible with conventional darlington phototransistor optocou-
pler. In the dual channel devices, HCPL-2730/HCPL2731, an
integrated emitter - base resistor provides superior stability over
temperature.
The combination of a very low input current of 0.5 mA and a
high current transfer ratio of 2000% makes this family particu-
larly useful for input interface to MOS, CMOS, LSTTL and EIA
RS232C, while output compatibility is ensured to CMOS as well
as high fan-out TTL requirements. An internal noise shield pro-
vides exceptional common mode rejection of 10 kV/µs.
Applications
■
Digital logic ground isolation
■
Telephone ring detector
■
EIA-RS-232C line receiver
■
High common mode noise line receiver
■
µP bus isolation
■
Current loop receiver
Package
Schematic
N/C 1
8 V
CC
+ 1
V
F1
8 V
CC
8
1
+ 2
V
F
_
3
7 V
B
_ 2
7 V
01
6 V
O
_
V
F2
3
6 V
02
N/C 4
5 GND
+ 4
5 GND
8
1
8
1
6N138 / 6N139
HCPL-2730 / HCPL-2731
1
©2005 Fairchild Semiconductor Corporation
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.2
www.fairchildsemi.com
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers
Absolute Maximum Ratings
(T
A
= 25°C unless otherwise specified)
Parameter
Storage Temperature
Operating Temperature
Lead Solder Temperature (Wave solder only. See recommended reflow profile graph for
SMD mounting)
EMITTER
DC/Average Forward Input Current
Peak Forward Input Current (50% duty cycle, 1 ms P.W.)
Peak Transient Input Current - (
≤
1 µs P.W., 300 pps)
Reverse Input Voltage
Input Power Dissipation
DETECTOR
Average Output Current
Emitter-Base Reverse Voltage
Supply Voltage, Output Voltage
Each Channel
(6N138 and 6N139)
(6N138, HCPL-2730)
(6N139, HCPL-2731)
Output Power Dissipation
Each Channel
P
O
I
O
(avg)
V
ER
V
CC
, V
O
60
0.5
-0.5 to 7
-0.5 to 18
100
mW
mA
V
V
Each Channel
Each Channel
Each Channel
Each Channel
I
F
(avg)
I
F
(pk)
I
F
(trans)
V
R
P
D
20
40
1.0
5
35
mA
mA
A
V
mW
Symbol
T
STG
T
OPR
T
SOL
Value
-55 to +125
-40 to +85
260 for 10 sec
Units
°C
°C
°C
Electrical Characteristics
(T
A
= 0 to 70°C Unless otherwise specified)
Individual Component Characteristics
Parameter
EMITTER
Input Forward Voltage
Input Reverse Breakdown Voltage
Test Conditions Symbol
T
A
=25°C
Each channel (I
F
= 1.6 mA)
(T
A
= 25°C, I
R
= 10 µA)
Each Channel
BV
R
(
∆
V
F
/
∆
T
A
)
I
OH
V
F
Device
All
Min Typ** Max
1.30
1.7
1.75
Unit
V
All
5.0
20
V
Temperature coefficient of forward voltage (I
F
= 1.6 mA)
DETECTOR
Logic high output current
(I
F
= 0 mA, V
O
= V
CC
= 18 V)
Each Channel
(I
F
= 0 mA, V
O
= V
CC
= 7 V)
Each Channel
Logic low supply
(I
F
= 1.6 mA, V
O
= Open)
(V
CC
= 18 V)
(I
F1
= I
F2
= 1.6 mA, V
CC
= 18 V)
(V
O1
- V
O2
= Open, V
CC
= 7 V
Logic high supply
(I
F
= 0 mA, V
O
= Open,
V
CC
= 18 V)
(I
F1
= I
F2
= 0 mA, V
CC
= 18 V)
(V
O1
- V
O2
= Open, V
CC
= 7 V
** All Typicals at T
A
= 25°C
All
-1.8
mV/°C
6N139
HCPL-2731
6N138
HCPL-2730
0.01
100
µA
0.01
250
I
CCL
6N138
6N139
HCPL-2731
HCPL-2730
0.4
1.3
1.5
3
mA
I
CCH
6N135
6N136
HCPL-2731
HCPL-2730
0.05
0.10
10
20
µA
2
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.2
www.fairchildsemi.com
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers
Transfer Characteristics
(T
A
= 0 to 70°C Unless otherwise specified)
Parameter
COUPLED
Current transfer ratio
(Note 1, 2)
Test Conditions Symbol
(I
F
= 0.5 mA, V
O
= 0.4 V, V
CC
= 4.5 V)
Each Channel
(I
F
= 1.6 mA, V
O
= 0.4 V, V
CC
= 4.5 V)
Each Channel
(I
F
= 1.6 mA, V
O
= 0.4 V, V
CC
= 4.5 V)
Each Channel
CTR
Device
6N139
HCPL-2731
6N139
HCPL-2731
6N138
HCPL-2730
Min
400
Typ**
1100
3500
Max
Unit
%
500
1300
2500
%
300
1300
2500
0.08
0.01
0.4
0.4
%
Logic low output voltage
output voltage (Note 2)
(I
F
= 0.5 mA, I
O
= 2 mA, V
CC
= 4.5 V)
(I
F
= 1.6 mA, I
O
= 8 mA, V
CC
= 4.5 V)
Each Channel
(I
F
= 0.5 mA, I
O
= 15 mA, V
CC
= 4.5 V)
Each Channel
(I
F
= 12 mA, I
O
= 24 mA, V
CC
= 4.5 V)
Each Channel
(I
F
= 1.6 mA, I
O
= 4.8 mA, V
CC
= 4.5 V)
Each Channel
V
OL
6N139
6N139
HCPL-2731
6N139
HCPL-2731
6N139
HCPL-2731
6N138
HCPL-2730
V
0.13
0.4
0.20
0.4
0.10
0.4
** All Typicals at T
A
= 25°C
3
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.2
www.fairchildsemi.com
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers
Switching Characteristics
(T
A
= 0 to 70°C unless otherwise specified., V
CC
= 5 V)
Parameter
Propagation delay
time to logic low
(Note 2) (Fig. 22)
Test Conditions Symbol
(R
L
= 4.7 k
Ω
, I
F
= 0.5 mA)
T
A
= 25°C
(R
L
= 4.7 k
Ω
, I
F
= 0.5 mA)
Each Channel
T
A
= 25°C
(R
L
= 270
Ω
, I
F
= 12 mA)
T
A
= 25°C
(R
L
= 270
Ω,
I
F
= 12 mA)
Each Channel
T
A
= 25°C
T
A
= 25°C
(R
L
= 2.2 kΩ, I
F
= 1.6 mA)
Each Channel
T
A
= 25°C
T
PLH
Each Channel
(R
L
= 4.7 kΩ, I
F
= 0.5 mA) T
A
= 25°C
Each Channel
(R
L
= 270
Ω,
I
F
= 12 mA)
T
A
= 25°C
(R
L
= 270
Ω,
I
F
= 12 mA) Each Channel
T
A
= 25°C
(R
L
= 2.2 kΩ, I
F
= 1.6 mA)
Each Channel
(R
L
= 2.2 kΩ, I
F
= 1.6 mA) T
A
= 25°C
Each Channel
(R
L
= 2.2 kΩ, I
F
= 1.6 mA)
T
PHL
Device
6N139
Min
Typ** Max Unit
30
4
25
120
3
100
2
0.2
1
3
0.3
2
15
1.5
10
25
1
20
90
µs
µs
HCPL-2731
6N139
HCPL-2730
HCPL-2731
6N138
HCPL-2731
HCPL-2730
6N139
HCPL-2731
6N139
HCPL-2731
6N139
Propagation delay
time to logic high
(Note 2) (Fig. 22)
(R
L
= 4.7 kΩ, I
F
= 0.5 mA)
12
22
60
10
1.3
7
15
5
10
50
HCPL-2730
HCPL-2731
6N138
HCPL-2730/1
6N138
HCPL-2730/1
|CM
H
|
6N138
6N139
HCPL-2730
HCPL-2731
|CM
L
|
6N138
6N139
HCPL-2730
HCPL-2731
1,000
1,000
7
16
10,000
35
Common mode
transient immunity
at logic high
(I
F
= 0 mA, |V
CM
| = 10 V
P-P
)
T
A
= 25°C, (R
L
= 2.2 kΩ) (Note 3) (Fig. 23)
Each Channel
(I
F
= 1.6 mA, |V
CM
| = 10 V
P-P
, R
L
= 2.2 kΩ)
T
A
= 25°C, (Note 3) (Fig. 23)
Each Channel
V/µs
Common mode
transient immunity
at logic low
10,000
V/µs
** All Typicals at T
A
= 25°C
4
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.2
www.fairchildsemi.com
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers
Isolation Characteristics
(T
A
= 0 to 70°C Unless otherwise specified)
Characteristics
Input-output
insulation leakage current
Test Conditions Symbol
(Relative humidity = 45%)
(T
A
= 25°C, t = 5 s)
(V
I-O
= 3000 VDC)
(Note 8)
(RH
≤
50%, T
A
= 25°C, I
I-O
≤
2 µA)
(Note 4) ( t = 1 min.)
(Note 4) (V
I-O
= 500 VDC)
(Note 4, 5) (f = 1 MHz)
(RH
≤
45%, V
I-I
= 500 VDC) (Note 6)
t = 5 s, (HCPL-2730/2731 only)
(V
I-I
= 500 VDC) (Note 6)
(HCPL-2730/2731 only)
(f = 1 MHz) (Note 6)
(HCPL-2730/2731 only)
I
I-O
Min
Typ**
Max
1.0
Unit
µA
Withstand insulation test voltage
Resistance (input to output)
Capacitance (input to output)
Input-Input
Insulation leakage current
Input-Input Resistance
Input-Input Capacitance
V
ISO
R
I-O
C
I-O
I
I-I
R
I-I
C
I-I
2500
10
12
0.6
0.005
10
11
0.03
V
RMS
Ω
pF
µA
Ω
pF
** All Typicals at T
A
= 25°C
Notes
1. Current Transfer Ratio is defined as a ratio of output collector current, I
O
, to the forward LED input current, I
F
, times 100%.
2. Pin 7 open. (6N138 and 6N139 only)
3. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
cm
/dt on the leading edge of the com-
mon mode pulse signal V
CM
, to assure that the output will remain in a logic high state (i.e., V
O
>2.0 V). Common mode transient
immunity in logic low level is the maximum tolerable (negative) dV
cm
/dt on the trailing edge of the common mode pulse signal,
V
CM
, to assure that the output will remain in a logic low state (i.e., V
O
<0.8 V).
4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
5. For dual channel devices, C
I-O
is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shorted
together.
6. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
I
5
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.2
www.fairchildsemi.com
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