TECHNICAL DATA
IN74LV00
Quad 2-Input NAND Gate
The IN74LV00 is low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT00A.
The IN74LV00 provides the 2-Input NAND function.
•
•
•
Optimized for Low Voltage applications: 1.2 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low Input Current
ORDERING INFORMATION
IN74LV00N
Plastic
IN74LV00D
SOIC
IZ74LV00
Chip
T
A
= -40° ? 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
01
02
04
05
09
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
2Y
1Y
03
06
3Y
08
FUNCTION TABLE
4Y
11
A
L
PIN 14 =V
CC
PIN 7 = GND
L
H
H
H - high level
L - low level
Input
B
L
H
L
H
Output
Y
=
A *B
H
H
H
L
INTEGRAL
1
IN74LV00
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
Tstg
T
L
*
Parameter
DC supply voltage (Referenced to GND)
DC input diode current
DC output diode current
DC output source or sink current
-bus driver outputs
DC V
CC
current for types with
- bus driver outputs
DC GND current for types with
- bus driver outputs
Power dissipation per package, plastic DIP+
SOIC package+
Storage temperature
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
Value
-0.5
÷
+5.0
±20
±50
±25
±50
±50
750
500
-65
÷
+150
260
Unit
V
mA
mA
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
1
* : V
I
<
-0.5 or V
I
>
V
CC
+0.5V
*
2
: Vo
<
-0.5 or Vo
>
V
CC
+0.5V
*
3
: -0.5V
<
Vo
<
V
CC
+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
Min
1.2
0
-40
0
0
0
0
Max
3.6
V
CC
+125
1000
700
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
INTEGRAL
2
IN74LV00
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
LH
= t
HL
= 6.0 ns, V
IL
=0V, V
IH
=V
CC
)
Symbol
Parameter
V
CC
V
min
t
THL,
(t
TLH
)
Output Transition
Time, Any Output
(Figure 1)
Propagation Delay,
Input A to Output Y
(Figure 1)
Input Capacitance
1.2
2.0
*
1.2
2.0
*
3.0
-
-
-
-
-
-
25°C
max
60
16
10
135
23
14
7.0
Guaranteed Limit
-40°C ? 85°C
min
-
-
-
-
-
-
-
max
75
20
13
405
28
18
-
-40°C ? 125°C
min
-
-
-
-
-
-
-
max
90
24
15
405
34
21
-
pF
ns
Unit
t
PHL,
(t
PLH
)
C
I
C
PD
Power Dissipation Capacitance (Per Inverter)
Ò
À
=25°Ñ, V
I
=0V?V
CC
pF
44
* - V
CC
= (3.3±0.3) V
Used to determine the no-load dynamic power consumption:
P
D
= C
PD
V
CC2
f
I
+ ?(C
L
V
CC2
fo), f
I
-input frequency, fo- output frequency (MHz)
?(C
L
V
CC2
fo) – sum of the outputs
t
HL
0.9
t
LH
0.9
V
1
0.1
0.1
V
1
V
CC
GND
Input À, B
t
P LH
t
PHL
V
CC
V
1
0.1
0.9
0.9
Output Y
0.1
V
1
t
TLH
V
1
= 0.5 V
CC
t
THL
GND
Figure 1. Switching Waveforms
V
CC
V
I
PULSE
GENERATOR
R
T
DEVICE
UNDER
TEST
V
O
C
L
R
L
Termination resistance R
T
-
should be equal to Z
OUT
pulse
generators
Figure 2. Test Circuit
INTEGRAL
4
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