TECHNICAL DATA
IN7406
Hex Inverter Buffers/Drivers with
Open-Collector High-Voltage
Outputs
The IN7406 monolithic TTL hex inverter buffers/drivers feature
high-voltage open collector outputs for interfacing with high-level
circuits (such as MOS) or for driving high-current loads (such as lamps
or relays), and are also characterized for use as inverter buffers for
driving TTL inputs.
•
•
•
•
•
Minimum breakdown Voltages is 30 V
Maximum sink Current is 40 mÀ
Converts TTL Voltage Levels to MOS Levels
Open-Collector Driver for Indicator Lamps and Relays
Inputs Fully Compatible with MOST TTL Circuits.
ORDERING INFORMATION
IN7406N Plastic
IN7406D SOIC
IZ7406
Chip
T
A
= -10° to 70° C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
A
L
H
Z = High Impedance
Output
Y
Z
L
Y=A
PIN 14 =V
CC
PIN 7 = GND
INTEGRAL
1
IN7406
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
Tstg
*
Parameter
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Value
7.0
5.5
30
-65 to +150
Unit
V
V
V
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IH
V
IL
U
OH
I
OL
T
A
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Current
Ambient Temperature Range
-10
Parameter
Min
4.75
2.0
0.8
30
40
+70
Max
5.25
Unit
V
V
V
V
mA
°C
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit
Symbol
V
IK
I
OH
V
OL
Parameter
Input Clamp Voltage
High Level Output Current
Low Level Output Voltage
Test Conditions
V
CC
= 4.75V, I
IN
= -12 mA
V
CC
= 4.75V, V
OH
=30V
V
CC
= 4.75V, I
OL
= 16 mA
V
CC
= 4.75V, I
OL
= 40 mA
I
IH
I
IL
I
CC
High Level Input Current
V
CC
= 5.25V, V
IN
= 2.4 V
V
CC
= 5.25V, V
IN
= 0.4 V
V
CC
= 5.25V
Outputs High
Outputs Low
Min
Max
-1.5
0.25
0.4
0.7
0.04
mA
Unit
V
mA
V
Low Level Input Current
Supply Current
-1.6
48
51
mA
mA
INTEGRAL
2
IN7406
AC ELECTRICAL CHARACTERISTICS
(T = 25°C, V
CC
= 5.0 V, C
L
= 15 pF,
R
L
= 110
Ω,
Input t
r
= t
f
= 10 ns)
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay Time, Low to High Level Output (from
Input to Output)
Propagation Delay Time, High to Low Level Output (from
Input to Output)
Min
Max
18
28
Unit
ns
ns
Figure 1. Switching Waveforms
* Includes all probe and jig capacitance
Figure 2. Test Circuit
INTEGRAL
3
IN7406
CHIP PAD DIAGRAM IZ7406
12
13
11
10
09
08
07
Chip marking
ËÍ3
01
02
(0,0)
03
04
06
05
1.45
±
0.03
Pad size 0.140 x 0.140 mm (Pad size is given as per metallization layer)
Thickness of chip 0,46±0,02 mm
PAD LOCATION
Pad No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
Symbol
A1
Y1
A2
Y2
A3
Y3
GND
Y4
A4
Y5
A5
Y6
A6
V
CC
X
0.090
0.090
0.460
0.830
1.220
1.220
1.220
1.220
1.220
0.830
0.460
0.090
0.090
0.090
Y
0.380
0.090
0.090
0.090
0.090
0.380
0.630
0.880
1.170
1.170
1.170
1.170
0.880
0.630
INTEGRAL
4
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