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HCF4006M013TR: 产品描述18-STAGE STATIC SHIFT REGISTER; 产品类别逻辑逻辑; 文件大小123KB，共8页; 制造商ST(意法半导体); 官网地址http://www.st.com/; 标准

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HCF4006M013TR概述

18-STAGE STATIC SHIFT REGISTER

HCF4006M013TR规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	ST(意法半导体)
零件包装代码	SOIC
包装说明	SOP-14
针数	14
Reach Compliance Code	compli
其他特性	SHARED CLOCK BETWEEN 4 SHIFT REGISTERS; TWO 4 BIT & TWO 5 BIT SHIFT REGISTERS
计数方向	RIGHT
系列	4000/14000/40000
JESD-30 代码	R-PDSO-G14
JESD-609代码	e4
长度	8.65 mm
负载电容（CL）	50 pF
逻辑集成电路类型	SERIAL IN SERIAL OUT
湿度敏感等级	1
位数	5
功能数量	4
端子数量	14
最高工作温度	125 °C
最低工作温度	-55 °C
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装等效代码	SOP14,.25
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
峰值回流温度（摄氏度）	260
电源	5/15 V
认证状态	Not Qualified
座面最大高度	1.75 mm
最大供电电压 (Vsup)	20 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
触发器类型	NEGATIVE EDGE
宽度	3.9 mm

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HCF4006B

18-STAGE STATIC SHIFT REGISTER

PERMANENT REGISTER STORAGE WITH

CLOCK LINE "HIGH" OR "LOW" ... NO

INFORMATION RECIRCULATION

REQUIRED

FULLY STATIC OPERATION

SHIFTING RATES UP TO

12MHzat 10V (Typ.)

STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

QUIESCENT CURRENT SPECIFIED UP TO

20V

5V, 10V AND 15V PARAMETRIC RATINGS

INPUT LEAKAGE CURRENT

= 100nA (MAX) AT V

= 18V T

= 25°C

100% TESTED FOR QUIESCENT CURRENT

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B " STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DIP

SOP

ORDER CODES

PACKAGE

DIP

SOP

TUBE

HCF4006BEY

HCF4006BM1

T&R

HCF4006M013TR

DESCRIPTION

The HCF4006B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.

The HCF4006B is comprised of 4 separate "shift

two sections of five stages with an output tap at

the fourth stage. Each section has an independent

"single rail" data path. A common clock signal is

used for all stages. Data is shifted to the next

stage on negative going transitions of the clock.

Through appropriate connections of inputs and

outputs, multiple register sections of 4, 5, 8 and 9

stages or single register sections of 10, 12, 13, 14,

16, 17 and 18 can be implemented using one

HCF4006B package. Longer shift register

sections can be assembled by using more than

one HCF4006B. To facilitate cascading stages

when clock rise and fall times are slow, an optional

output (D1+4’) that is delayed one-half

clock-cycle, is provided (see truth table for output

from pin 2)

PIN CONNECTION

September 2001

1/8

推荐资源

PS21、700X/700Y、WT112图二

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