M2716
NMOS 16 Kbit (2Kb x 8) UV EPROM
NOT FOR NEW DESIGN
s
s
2048 x 8 ORGANIZATION
525mW Max ACTIVE POWER, 132mW Max
STANDBY POWER
ACCESS TIME:
– M2716-1 is 350ns
– M2716 is 450ns
24
s
s
s
s
SINGLE 5V SUPPLY VOLTAGE
STATIC-NO CLOCKS REQUIRED
INPUTS and OUTPUTS TTL COMPATIBLE
DURING BOTH READ and PROGRAM
MODES
THREE-STATE OUTPUT with TIED-OR-
CAPABILITY
EXTENDED TEMPERATURE RANGE
PROGRAMMING VOLTAGE: 25V
Figure 1. Logic Diagram
1
FDIP24W (F)
s
s
s
DESCRIPTION
The M2716 is a 16,384 bit UV erasable and elec-
trically programmable memory EPROM, ideally
suited for applications where fast turn around and
pattern experimentation are important require-
ments.
The M2716 is housed in a 24 pin Window Ceramic
Frit-Seal Dual-in-Line package. The transparent
lid allows the user to expose the chip to ultraviolet
light to erase the bit pattern. A new pattern can
then be written to the device by following the pro-
gramming procedure.
VCC
VPP
11
A0-A10
8
Q0-Q7
EP
G
M2716
VSS
AI00784B
November 2000
This is information on a product still in production but not recommended for new designs.
1/9
M2716
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
BIAS
T
STG
V
CC
V
IO
V
PP
P
D
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Supply Voltage
Input or Output Voltages
Program Supply
Power Dissipation
grade 1
grade 6
grade 1
grade 6
Value
0 to 70
–40 to 85
–10 to 80
–50 to 95
–65 to 125
–0.3 to 6
–0.3 to 6
–0.3 to 26.5
1.5
Unit
°C
°C
°C
V
V
V
W
Note:
Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for ex tended periods
may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Figure 2. DIP Pin Connections
Deselect Mode.
The M2716 is deselected by mak-
ing G = V
IH
. This mode is independent of EP and
the condition of the addresses. The outputs are
Hi-Z when G = V
IH
. This allows tied-OR of 2 or more
M2716’s for memory expansion.
VCC
A8
A9
VPP
G
A10
EP
Q7
Q6
Q5
Q4
Q3
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
M2716
24
23
22
21
20
19
18
17
16
15
14
13
AI00785
Standby Mode (Power Down).
The M2716 may
be powered down to the standby mode by making
EP = V
IH
. This is independent of G and automat-
ically puts the outputs in the Hi-Z state. The power
is reduced to 25% (132 mW max) of the normal
operating power. V
CC
and V
PP
must be maintained
at 5V. Access time at power up remains either t
AVQV
or t
ELQV
(see Switching Time Waveforms).
Programming
The M2716 is shipped from SGS-THOMSON com-
pletely erased. All bits will be at “1" level (output
high) in this initial state and after any full erasure.
Table 3 shows the 3 programming modes.
Program Mode.
The M2716 is programmed by
introducing “0"s into the desired locations. This is
done 8 bits (a byte) at a time. Any individual address,
sequential addresses, or addresses chosen at ran-
dom may be programmed. Any or all of the 8 bits
associated with an address location may be pro-
grammed with a single program pulse applied to the
EP pin. All input voltage levels including the program
pulse on chip enable are TTL compatible.
The programming sequence is: with V
PP
= 25V, V
CC
= 5V, G = V
IH
and EP = V
IL
, an address is selected
and the desired data word is applied to the output
pins (V
IL
= “0" and V
IH
= ”1" for both address and
data). After the address and data signals are stable
the program pin is pulsed from V
IL
to V
IH
with a
DEVICE OPERATION
The M2716 has 3 modes of operation in the normal
system environment. These are shown in Table 3.
Read Mode.
The M2716 read operation requires
that G = V
IL
, EP = V
IL
and that addresses A0-A10
have been stabilized. Valid data will appear on the
output pins after time t
AVQV
, t
GLQV
or t
ELQV
(see
Switching Time Waveforms) depending on which is
limiting.
2/9
M2716
DEVICE OPERATION
(cont’d)
pulse width between 45ms and 55ms. Multiple
pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(V
IH
or higher) must not be maintained longer than
t
PHPL
(max) on the program pin during program-
ming. M2716’s may be programmed in parallel in
this mode.
Program Verify Mode.
The programming of the
M2716 may be verified either one byte at a time
during the programming (as shown in Figure 6) or
by reading all of the bytes out at the end of the
programming sequence. This can be done with
V
PP
= 25V or 5V in either case. V
PP
must be at 5V
for all operating modes and can be maintained at
25V for all programming modes.
Program Inhibit Mode.
The program inhibit mode
allows several M2716’s to be programmed simul-
taneously with different data for each one by con-
trolling which ones receive the program pulse. All
similar inputs of the M2716 may be paralleled.
Pulsing the program pin (from V
IL
to V
IH
) will pro-
gram a unit while inhibiting the program pulse to a
unit will keep it from being programmed and keep-
ing G = V
IH
will put its outputs in the Hi-Z state.
ERASURE OPERATION
The M2716 is erased by exposure to high intensity
ultraviolet light through the transparent window.
This exposure discharges the floating gate to its
initial state through induced photo current. It is
recommended that the M2716 be kept out of direct
sunlight. The UV content of sunlight may cause
a partial erasure of some bits in a relatively short
period of time.
An ultraviolet source of 2537 Å yielding a total
integrated dosage of 15 watt-seconds/cm
2
power
rating is used. The M2716 to be erased should be
placed 1 inch away from the lamp and no filters
should be used.
An erasure system should be calibrated peri-
odically. The erasure time is increased by the
square of the distance (if the distance is doubled
the erasure time goes up by a factor of 4). Lamps
lose intensity as they age, it is therefore important
to periodically check that the UV system is in good
order.
This will ensure that the EPROMs are being com-
pletely erased. Incomplete erasure will cause
symptoms that can be misleading. Programmers,
components, and system designs have been erro-
neously suspected when incomplete erasure was
the basic problem.
Table 3. Operating Modes
Mode
Read
Program
Verify
Program Inhibit
Deselect
Standby
Note:
X = V
IH
or V
IL
.
EP
V
IL
V
IH
Pulse
V
IL
V
IL
X
V
IH
G
V
IL
V
IH
V
IL
V
IH
V
IH
X
V
PP
V
CC
V
PP
V
PP
or V
CC
V
PP
V
CC
V
CC
Q0 - Q7
Data Out
Data In
Data Out
Hi-Z
Hi-Z
Hi-Z
3/9
M2716
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
20ns
0.45V to 2.4V
0.8V to 2.0V
Figure 4. AC Testing Load Circuit
1.3V
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
2.4V
DEVICE
UNDER
TEST
CL = 100pF
OUT
2.0V
0.8V
AI00827
0.45V
CL includes JIG capacitance
AI00828
Table 4. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note:
1. Sampled only, not 100% tested.
Table 5. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
PP
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby)
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1mA
I
OH
= –400µA
2.4
Test Condition
0
≤
V
IN
≤
V
CC
V
OUT
= V
CC
, EP = V
CC
EP = V
IL
, G = V
IL
EP = V
IH
, G = V
IL
V
PP
= V
CC
–0.1
2
Min
Max
±10
±10
100
25
5
0.8
V
CC
+ 1
0.45
Unit
µA
µA
mA
mA
mA
V
V
V
V
Note:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
4/9
M2716
Table 6. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
M2716
Symbol
Alt
Parameter
Test Condition
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
(2)
(2)
-1
Max
350
350
120
0
0
0
100
100
0
0
0
blank
Min
Max
450
450
120
100
100
Unit
t
ACC
t
CE
t
OE
t
OD
t
DF
t
OH
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
EP = V
IL
, G = V
IL
G = V
IL
EP = V
IL
G = V
IL
EP = V
IL
EP = V
IL
, G = V
IL
ns
ns
ns
ns
ns
ns
t
AXQX
Notes:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A10
tAVQV
EP
tGLQV
G
tELQV
Q0-Q7
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
DATA OUT
AI00786
Table 7. Programming Mode DC Characteristics
(1)
(T
A
= 25
°C;
V
CC
= 5V
±
5%; V
PP
= 25V
±
1V)
Symbol
I
LI
I
CC
I
PP
I
PP1
V
IL
V
IH
Parameter
Input Leakage Current
Supply Current
Program Current
Program Current Pulse
Input Low Voltage
Input High Voltage
EP = V
IH
Pulse
–0.1
2
Test Condition
V
IL
≤
V
IN
≤
V
IH
Min
Max
±10
100
5
30
0.8
V
CC
+ 1
Unit
µA
mA
mA
mA
V
V
Note:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
5/9
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