Si5020
SiPHY™ M
ULTI
-R
ATE
SONET/SDH C
LOCK
Features
Complete high speed, low power, CDR solution includes the following:
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AND
D
ATA
R
ECOVERY
IC
Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
Low Power—270 mW (TYP OC-48)
Small Footprint: 4 mm x 4 mm
DSPLL™ Eliminates External Loop
Filter Components
3.3 V Tolerant Control Inputs
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!
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Exceeds All SONET/SDH
Jitter Specifications
Jitter Generation
3.0 mUI
RMS
(TYP)
Device Power Down
Loss-of-Lock Indicator
Single 2.5 V Supply
Ordering Information:
See page 14.
Applications
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RATESEL1
RATESEL0
CLKOUT+
Description
REXT
20 19 18
1
2
3
4
5
6
LOL
GND
!
17 16
15
PWRDN/CAL
14
VDD
The Si5020 is a fully integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1,
or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also
provided for OC-48/STM-16 applications that employ forward error
correction (FEC). DSPLL™ technology eliminates sensitive noise entry
points thus making the PLL less susceptible to board-level interaction and
helping to ensure optimal jitter performance.
The Si5020 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40°C to 85°C).
VDD
GND
REFCLK+
REFCLK–
GND
Pad
CLKOUT–
SONET/SDH/ATM Routers
Add/Drop Multiplexers
Digital Cross Connects
Gigabit Ethernet Interfaces
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SONET/SDH Test Equipment
Optical Transceiver Modules
SONET/SDH Regenerators
Board Level Serial Links
Pin Assignments
Si5020
13
DOUT+
12
DOUT–
11
VDD
7
VDD
8
GND
9
DIN+
10
DIN–
Top View
Functional Block Diagram
LOL
DIN+
DIN–
2
BUF
DSPLL™
Phase-Locked
Loop
Retimer
BUF
2
DOUT+
DOUT–
PWRDN/CAL
Bias
2
2
BUF
2
CLKOUT+
CLKOUT–
REXT
RATESEL1–0
REFCLK+
REFCLK–
Preliminary Rev. 0.8 12/00
Copyright © 2000 by Silicon Laboratories
Si5020-DS08
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
S i5 02 0
2
Preliminary Rev. 0.8
Si5020
T
A B L E O F
C
O N T E N T S
Section
Page
4
5
9
9
9
9
9
9
10
10
11
11
11
11
11
13
15
16
18
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions: Si5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.8
3
S i5 02 0
Detailed Block Diagram
R e tim e
DOUT+
DOUT–
c
D IN +
D IN –
Phase
D e te c to r
A /D
DSP
n
VCO
CLK
D ivid e r
CLKOUT+
c
CLKOUT–
REFCLK+
REFCLK–
Lock
D e te c to r
2
R A T E S E L 1-0
REXT
B ias
G en e ra tio n
C a lib ratio n
LOL
P W R D N /C A L
Figure 1. Detailed Block Diagram
4
Preliminary Rev. 0.8
Si5020
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5020 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
2.375
Typ
25
2.5
Max
1
85
2.625
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless
otherwise stated.
2.
The Si5020 specifications are guaranteed when using the recommended application circuit (including
component tolerance) of Figure 5 on page 9.
V
SIGNAL+
V
ICM
,V
OCM
Differential
I/Os
SIGNAL–
V
IS
Single-Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
V
ID
,V
OD
(V
ID
= 2V
IS
)
Differential Peak-to-Peak Voltage
t
Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t
C
f
-D
DOUT
t
Cr-D
CLKOUT
Figure 3. Clock to Data Timing
DOUT,
CLKOUT
80%
20%
t
F
t
R
Figure 4. DOUT and CLKOUT Rise/Fall Times
Preliminary Rev. 0.8
5
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