100/200Mbps speeds and performs cable interface and
bus arbitration. It conforms to the high performance seri-
al bus IEEE1394-1995 standard. The structure is 0.4µm
CMOS and it operates on a single 3.3V power supply.
64 pin LQFP (plastic)
Features
• Conforms to IEEE1394-1995
• Single 3.3V power supply
• Supports 100/200Mbps speeds
• Automatic power down for unused ports
• Power down mode to conserve energy
• Supports short reset operation
• Supports ping for optimization of a Gap_count
Absolute Maximum Ratings
• Supply voltage
• Input voltage
• Output voltage
• Storage temperature
V
DD
V
I
–0.5 to +4.6
V
Applications
When used with a LINK chip (e.g. CXD1940R), allows
configuration of a high-speed digital serial interface.
Structure
0.4µm CMOS monolithic IC
1000
mW
V
SS
–0.5 to V
DD
+0.5 V
–20 to +70
–55 to +150
°C
°C
Package
64-pin plastic LQFP (VQFP)
Operating Conditions
• Supply voltage
V
DD
3.0 to 4.5
–20 to +75
V
°C
• Operating temperature Ta
V
O
V
SS
–0.5 to V
DD
+0.5 V
Tstg
P
D
• Operating temperature Ta
• Allowable power dissipation
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE96431–ST
CXD1944R
Block Diagram
CMC/LKON
PC0
PC1
PC2
TIO
TEST0
TEST1
LDSEL
CPS
LPS
XISO
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
Arbitration
and Control
State Machine
Logic
Link
Interface
I/O
Cable Port 2
TPB2+
TPB2–
TPA3+
TPA3–
Cable Port 3
TPB3+
TPB3–
TB1
TB2
TB3
R1
R0
XI
XO
FLT
TPA1+
TPA1–
Cable Port 1
TPB1+
TPB1–
TPA2+
TPA2–
Received Data
Decoder and
Retimer
Voltage and
Current
Generator
Crystal
Oscillator PLL
System and
Transmit Clock
Generator
XRESET
Transmit Data
Encoder
–2–
CXD1944R
Pin Configuration
55 PLLV
DD
53 PLLV
SS
52 PLLV
SS
58 DV
DD
51 AV
DD
64 AV
SS
63 AV
SS
61 AV
SS
50 AV
SS
49 AV
SS
48 TB3
47 TB2
46 TB1
45 TPA1+
44 TPA1–
43 TPB1+
42 TPB1–
41 AV
SS
40 TPA2+
39 TPA2–
38 TPB2+
37 TPB2–
36 TPA3+
35 TPA3–
34 TPB3+
33 TPB3–
CAP 17
TIO 18
XSLOW 19
DV
DD
20
TEST1 21
TEST0 22
CPS 23
AV
DD
24
AV
DD
25
AV
SS
26
CMC/LKON 27
PC0 28
PC1 29
PC2 30
CNA 31
AV
SS
32
62 XISO
XRESET
LPS
LREQ
V
DD-IO
LDSEL
DV
DD
PWD
DV
SS
SYSCLK
1
2
3
4
5
6
7
8
9
DV
SS
10
CTL0 11
CTL1 12
D0 13
D1 14
D2 15
D3 16
–3–
54 FLT
57 XO
60 R1
59 R0
56 XI
CXD1944R
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Symbol
XRESET
LPS
LREQ
V
DD-IO
LDSEL
DV
DD
PWD
DV
SS
SYSCLK
DV
DD
CTL0
CTL1
D0
D1
D2
D3
CAP
TIO
XSLOW
DVDD
TEST1
TEST0
CPS
AV
DD
AV
DD
AV
SS
CMC/LKON
I/O
I
I
I
Supply
I
Supply
I
Supply
OUT
Supply
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
Supply
I
I
I(A)
Supply
Supply
Supply
I/O
Description
Reset input. Asserts at LOW. A power-on reset signal can be generated by
adding a 0.1µF capacitor.
LINK power supply status. LINK power supply is connected.
LINK request input.
IO power supply.
LINK delay select.
Digital circuit power supply.
Power down input.
Digital circuit ground.
System clock output; 49.152MHz clock to LINK.
Digital circuit power supply.
I/O of bidrectional control signals for LINK.
I/O of bidrectional control signals for LINK.
I/O of bidirectional data signals for LINK.
I/O of bidirectional data signals for LINK.
I/O of bidirectional data signals for LINK.
I/O of bidirectional data signals for LINK.
Connect to ground via 0.1µF capacitor when a 5V LINK is used.
Connect to V
SS
or V
DD
. If then connected to V
DD
, short reset mode is
selected.
When XSLOW = LOW, a device acts as a 100M PHY. Normally connected
to V
DD
.
Digital power supply.
Test mode control. Normally connected to ground.
Test mode control. Normally connected to ground.
Cable power status input. Normally connected to cable power.
Analog circuit power supply.
Analog circuit power supply.
Analog circuit power ground.
Configuration Manager Capable input, LINK ON clock (6MHz) output.
When LPS = LOW and a LinkOn packet is received, the 6MHz clock
signal continues to be output. Connect to V
DD
or V
SS
with a 10KΩ resister.
The configuration management function is indicated when connected to
V
DD
.
Power Class input (LSB).
Power Class input.
Power Class input (MSB).
Cable Not Active output. This output is debounced.
Analog circuit power ground.
Port3, Cable Pair B–.
Port3, Cable Pair B+.
28
29
30
31
32
33
34
PC0
PC1
PC2
CNA
AV
SS
TPB3–
TPB3+
I
I
I
O
Supply
I/O(A)
I/O(A)
–4–
CXD1944R
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
TPA3–
TPA3+
TPB2–
TPB2+
TPA2–
TPA2+
AV
SS
TPB1–
TPB1+
TPA1–
TPA1+
TB1
TB2
TB3
AV
SS
AV
SS
AV
DD
PLLV
SS
PLLV
SS
FLT
PLLV
DD
XI
XO
DV
DD
R0
R1
AV
SS
XISO
AV
SS
AV
SS
I/O
I/O(A)
I/O(A)
I/O(A)
I/O(A)
I/O(A)
I/O(A)
Supply
I/O(A)
I/O(A)
I/O(A)
I/O(A)
O(A)
O(A)
O(A)
Supply
Supply
Supply
Supply
Supply
O(A)
Supply
I(A)
O(A)
Supply
I(A)
O(A)
Supply
I
Supply
Supply
Port3, Cable Pair A–.
Port3, Cable Pair A+.
Port2, Cable Pair B–.
Port2, Cable Pair B+.
Port2, Cable Pair A–.
Port2, Cable Pair A+.
Analog circuit power ground.
Port1, Cable Pair B–.
Port1, Cable Pair B+.
Port1, Cable Pair A–.
Port1, Cable Pair A+.
Description
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power
down. Corresponds to one port.
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power
down. Corresponds to one port.
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power
down. Corresponds to one port.
Analog circuit power ground.
Analog circuit power ground.
Analog circuit power supply.
PLL circuit power ground.
PLL circuit power ground.
PLL loop filter.
PLL circuit power supply.
Crystal oscillator (24.576MHz±100ppm). The optimum values for the 100kΩ
resistor and 20pF capacitor.
Crystal oscillator (24.576MHz±100ppm). The optimum values for the 100kΩ
resistor and 20pF capacitor.
Digital circuit power supply.
Reference resistance pin. Connect R1 and R0 with 6.8kΩ±5% resistor. R0
may be connected to ground.
Reference resistance pin. Connect R1 and R0 with 6.8kΩ±5% resistor. R0
may be connected to ground.
Analog circuit power ground.
XISO = LOW indicates isolation barrier which enables digital differentiator.
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