HI-15530
5V / 3.3V Manchester Encoder / Decoder
August 2006
GENERAL DESCRIPTION
The HI-15530 is a high performance CMOS integrated
circuit designed to meet the requirements of MIL-STD-1553
and similar Manchester II encoded, time division
multiplexed serial data protocols. The HI-15530 contains
both an Encoder and Decoder, which operate
independently.
The HI-15530 is fully compatible with either 5V or 3.3V logic
and transceivers.
The device generates MIL-STD-1553 sync pulses, parity
bits as well as the Manchester II encoding of the data bits.
The decoder recognizes and identifies sync pulses,
decodes data bits, and performs parity checking.
The HI-15530 supports the 1Mbit/s data rate of MIL-STD-
1553 over the full temperature and voltage range.
For applications requiring small footprints and low cost, the
HI-15530 is available in a 24-pin plastic SSOP package.
Ceramic DIP and LCC packages are also available to
achieve the highest level of reliability and to provide drop-in
replacements for obsolete parts from other manufacturers.
FEATURES
!
MIL-STD-1553 compatible
!
5V or 3.3V operation
!
Interfaces to HI-1567 Transceiver Family
!
Small footprint 24-pin plastic SSOP package
option
!
Direct replacement for:
Harris/Intersil HD15530
GEC Plessey Semiconductors MAS15530
Aeroflex ACT15530
!
1.25 Mbit/s Maximum Data Rate
!
Manchester II Encode and Decode
!
Sync identification and Lock-in
PIN CONFIGURATION
(Top View)
VALID WORD
1
2
3
4
5
6
7
8
9
24 VDD
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
APPLICATIONS
!
MIL-STD-1553 Interfaces
!
Smart Munitions
!
Stores management
!
Sensor interfaces
!
Instrumentation
ENCODER SHIFT CLK
TAKE DATA
SERIAL DATA OUT
DECODER CLK
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
HI-15530PSI
HI-15530PST
HI-15530PSM
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15 BIPOLAR ZERO OUT
14
¸
6 OUT
13 MASTER RESET
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
24 Pin SSOP package
(See page 3-43 for additional Package Pin Configurations)
(DS15530 Rev. G)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/06
HI-15530
PIN DESCRIPTIONS
SIGNAL
VALID WORD
ENCODER SHIFT CLOCK
TAKE DATA
SERIAL DATA OUT
DECODER CLOCK
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLOCK
COMMAND / DATA SYNC
SECTION
DECODER
ENCODER
DECODER
DECODER
DECODER
DECODER
DECODER
DECODER
DECODER
DECODER
FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
DESCRIPTION
A high output signals the receipt of a valid word
Shifts data into the encoder on a low to high transition
Output is high during receipt of data after identification of a Sync
Pulse and two valid Manchester data bits.
Received Data output in NRZ format
12x the data rate. Clock for the transition finder and synchronizer,
which generates the internal clock for the remainder of the decoder
A high input indicates the 1553 bus is in its negative state.
This pin must be held high when the Unipolar input is used
A high input indicates the 1553 bus is in the positive state.
This pin must be held low when the Unipolar input is used
Input for unipolar data to the transition finder. Must be held low when
Not in use
Provides the DECODER CLOCK divided by 12, synchronized by the
recovered serial data
A high on this pin occurs during the output of decoded data which
was preceded by a Command (or Status) synchronizing character. A
low output indicates a Data synchronizing character
A high applied to this pin during a DECODER SHIFT CLOCK rising
edge resets the bit counter
0V supply
A high on this pin clears the 2:1 counters in both Encoder and
Decoder and resets the divide-by-6 circuit
Provides ENCODER CLOCK divided by 6
An active low output intended to drive the zero or negative sense of
a MIL-STD-1553 Line Driver
A low inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by
forcing them to inactive high states
An active low output intended to drive the one or positive sense on a
MIL-STD-1553 Line Driver
Accepts serial data at the rate of the ENCODER SHIFT CLOCK
A high on this pin initiates the encode cycle. (Subject to the
preceeding cycle being complete)
Actuates a Command Sync for an input high and a Data Sync for a
low
An active high output which enables the external source of serial
Data
Clock input at 2 times the Data rate, usually driven by
¸
6 OUT
Input to the divide by 6 circuit. Normal frequency is Data rate x12
3.0 V to 5.5 V power supply pin
DECODER RESET
GND
MASTER RESET
¸
6 OUT
BIPOLAR ZERO OUT
OUTPUT INHIBIT
BIPOLAR ONE OUT
SERIAL DATA IN
ENCODER ENABLE
SYNC SELECT
SEND DATA
SEND CLOCK IN
ENCODER CLOCK
VDD
DECODER
BOTH
BOTH
ENCODER
ENCODER
ENCODER
ENCODER
ENCODER
ENCODER
ENCODER
ENCODER
ENCODER
ENCODER
BOTH
INPUT
POWER
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
POWER
HOLT INTEGRATED CIRCUITS
2
HI-15530
ENCODER OPERATION
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide-by-six counter is provided on chip
which can be utilized to produce the SEND CLOCK by
dividing the ENCODER CLOCK.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK (1).
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a command sync or a low will produce a
data sync for that word (2). When the Encoder is ready to
accept data, the SEND DATA output will go high and
remain high for sixteen ENCODER SHIFT CLOCK periods
(3). During these sixteen periods the data should be
clocked into the SERIAL DATA IN input with every low-to-
high transition of the ENCODER SHIFT CLOCK (3) - (4).
After the sync and the Manchester II coded data are
transmitted through the BIPOLAR ONE and BIPOLAR
ZERO outputs, the Encoder adds on an additional bit which
is the parity for that word (5). If ENCODER ENABLE is held
high continuously, consecutive words will be encoded
without an interframe gap. ENCODER ENABLE must go
low by time (5) as shown to prevent a consecutive word
from being encoded. At any time a low on the OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low to high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new
word.
MASTER RESET
OUTPUT
INHIBIT
SEND CLK IN
¸
6 OUT
BIPOLAR
ONE OUT
¸2
¸6
Character
Former
ENCODER CLK
BIPOLAR
ZERO OUT
Bit
Counter
SYNC
SELECT
SEND
DATA
ENCODER
SHIFT
CLK
SERIAL
DATA
IN
ENCODER
ENABLE
FIGURE 1. ENCODER
TIMING
0
1
2
3
4
5
6
7
15
16
17
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
DON’T CARE
SYNC SELECT
VALID
DON’T CARE
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPLOAR
ZERO OUT
(1) (2)
15
14
13
12
11
10
3
2
1
0
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
(3)
(4) (5)
FIGURE 2. ENCODER OPERATION
HOLT INTEGRATED CIRCUITS
3
HI-15530
DECODER OPERATION
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The
BIPOLAR ONE and BIPOLAR ZERO inputs will accept
data from a comparator sensed transformer coupled bus as
specified in MIL-STD-1553. The UNIPOLAR DATA input
can only accept non-inverted Manchester II coded data
(e.g. from BIPOLAR ZERO OUT of an Encoder). The
Decoder is free running and continuously monitors its data
input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character was
a command sync, this output will go high (2) and remain
high for sixteen DECODER SHIFT CLOCK periods (3),
otherwise it will remain low. The TAKE DATA output will go
high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SERIAL DATA OUT.
The decoded data available at SERIAL DATA OUT is in an
NRZ format. The DECODER SHIFT CLOCK is provided so
that the decoded bits can be shifted into an external register
on every low-to-high transition of this clock (2) - (3). After all
sixteen decoded bits have been transmitted (3) the data is
checked for odd parity. A high on VALID WORD output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1). At any time in the above sequence, a
high input on DECODER RESET during a low-to-high
transition of DECODER SHIFT CLOCK will abort
transmission and initialize the Decoder to start looking for a
new sync character.
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
SERIAL DATA
OUT
TRANSITION
FINDER
CHARACTER
IDENTIFIER
COMMAND/DATA
SYNC
TAKE DATA
DECODER
CLK
MASTER
RESET
SYNCHRONIZER
BIT
RATE
CLK
PARITY
CHECK
VALID
WORD
DECODER
SHIFT CLK
DECODER
RESET
BIT
COUNTER
FIGURE 3. DECODER
TIMING
0
1
2
3
4
5
6
7
8
16
17
18
19
DECODER
SHIFT CLK
BIPOLAR
ONE IN
BIPLOAR
ZERO IN
SYNC
SYNC
15
14
13
12
11
10
2
1
0
P
SYNC
SYNC
15
14
13
12
11
10
2
1
0
P
TAKE DATA
COMMAND /
DATA SYNC
SERIAL
DATA OUT
UNDEFINED
15
14
13
12
4
3
2
1
0
VALID WORD
May be high from previous reception
(1)(2)
FIGURE 4. DECODER OPERATION
(3)
(4)
HOLT INTEGRATED CIRCUITS
4
HI-15530
TIMING DIAGRAMS
SEND CLK
t
E1
ENCODER
SHIFT CLK
t
E2
SERIAL DATA IN
VALID
VALID
t
E3
SEND CLK
ENCODER
SHIFT CLK
ENCODER ENABLE
t
E1
t
E4
t
E5
VALID
t
E7
t
E6
SYNC SELECT
ENCODER
SHIFT CLK
SEND DATA
t
E8
SEND CLK
t
E9
BIPOLAR ONE OUT or
BIPOLAR ZERO OUT
ENCODER TIMING
DECODER SHIFT CLK
t
D6
COMMAND / DATA SYNC
t
D7
TAKE DATA
DECODER SHIFT CLK
t
D8
SERIAL DATA OUT
DATA BIT
DECODER SHIFT CLK
t
D9
COMMAND / DATA SYNC
t
D10
TAKE DATA
t
D11
VALID WORD
DECODER SHIFT CLK
t
DRH
DECODER RESET
t
DR
t
DRS
DECODER TIMING
HOLT INTEGRATED CIRCUITS
5
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