HI-1575
February 2017
MIL-STD-1553 3.3V Dual Transceivers
with Integrated Encoder / Decoders
PIN CONFIGURATIONS
40 -
39 ERROR
38 CHA/CHB
37 CLK
36 D0
35 D1
34 D2
33 D3
32 D4
31 -
- 1
RCVA 2
BUSA 3
BUSA 4
VDD 5
BUSB 6
BUSB 7
RCVB 8
REG 9
- 10
DESCRIPTION
The HI-1575 is a low power CMOS dual transceiver with
on-chip Manchester II Encoder and dual Decoder
designed to meet the requirements of the MIL-STD-1553
specification. The part acts as a "Smart Transceiver",
allowing users to transmit and receive properly encoded
MIL-STD-1553 Command and Data words between a
16-bit host processor and dual MIL-STD-1553 data
buses.
A single write cycle is used to transfer a word to the
HI-1575, which encodes the data, adds the selected Sync
and Parity bits, and transmits the word on the chosen
MIL-STD-1553 data bus. Complete MIL-STD-1553
messages may be transmitted by executing multiple write
cycles to the device.
Activity on both MIL-STD-1553 data buses is continuously
monitored. When the HI-1575 detects a properly encoded
word, a hardware interrupt is generated and the
information is decoded and stored in one of two internal
registers, which may then be read by the host processor.
Bits in the internal Status & Mode Register indicate on
which bus the word was received and whether the word
had a Data or Command Sync.
1575PCI
1575PCT
30 -
29 D5
28 D6
27 D7
26 GND
25 D8
24 D9
23 D10
22 D11
21 -
40 Pin Plastic 6mm x 6mm
Chip-scale package
31 - CHA/CHB
32 - ERROR
30 - CLK
29 - D0
28 - D1
27 - D2
26 - D3
-
R/W
STRB
MR
SYNC
D15
D14
D13
D12
-
11
12
13
14
15
16
17
18
19
20
FEATURES
STRB - 10
SYNC - 12
D15 - 13
D14 - 14
D13 - 15
TQFP package
!
Less than 0.5W maximum power dissipation
!
6 mm x 6 mm 40-pin plastic chip-scale
package option
32 Pin TQFP package
(DS1575 Rev. E)
HOLT INTEGRATED CIRCUITS
www.holtic.com
R/W - 9
D12 - 16
MR - 11
!
Compliant to MIL-STD-1553A & B
!
3.3V single supply operation
!
On-chip Encoder and Dual Decoder
!
Small footprint available in 32-pin plastic
RCVA - 1
BUSA - 2
BUSA - 3
VDD - 4
BUSB - 5
BUSB - 6
RCVB - 7
REG - 8
25 - D4
24 - D5
23 - D6
HI-1575PQI
&
HI-1575PQT
22 - D7
21 - GND
20 - D8
19 - D9
18 - D10
17 - D11
02/17
HI-1575
PIN DESCRIPTIONS
PIN
(TQFP)
1
2
3
4
5,
6
7
8
9
10
11
12
13-20, 22-29
21
30
31
32
PULL-UP
SYMBOL FUNCTION PULL-DOWN
RCVA
BUSA
BUSA
VDD
BUSB
BUSB
RCVB
REG
R/W
STRB
MR
SYNC
D15:D0
GND
CLK
CHA/CHB
ERROR
Digital output
Analog I/O
Analog I/O
Power supply
Analog I/O
Analog I/O
Digital output
Digital input
Digital input
Digital input
Digital input
Digital I/O
Digital I/O
Power supply
Digital input
Digital Input
Digital output
-
-
-
-
-
-
-
12K pull-down
12K pull-up
12K pull-up
12K pull-down
12K pull-down
12K pull-down
-
-
12K pull-down
-
DESCRIPTION
Goes high when MIL-STD-1553 word received on Bus A
MIL-STD-1533 bus driver A, negative signal
MIL-STD-1553 bus driver A, positive signal
+3.3 VDC
MIL-STD-1533 bus driver B, negative signal
MIL-STD-1553 bus driver B, positive signal
Goes high when MIL-STD-1553 word received on Bus B
Selects Status & Mode Register when high, or Data registers when low
Controls data and sync direction during read or write operations
Strobe. Timing input to control register read and write operations
Pulse high to reset the HI-1575
Selects transmit sync type on write, indicates received sync type on read.
Data bus. D15 (MSB) corresponds to MIL-STD-1553 bit 4
Ground
12 MHz clock
Selects MIL-STD-1553 Bus A or Bus B
Goes high when a received MIL-STD-1553 word has an encoding error
FUNCTIONAL DESCRIPTION
Figure 1 shows a simplified block diagram of the HI-1575.
The MR (Master Reset) input should be pulsed high to
initialize the Manchester II Encoder and Decoders. MR
also clears the Receive Data registers, RXA and RXB,
and sets the Status & Mode register to its default state
as described in figure 2.
The CLK input requires a 12.0 MHz clock signal. CLK is
used to derive the 1.0 us bit period for MIL-STD-1553
data transmission, as well to provide the master clock for
the Manchester II encoder and the decoder's receiver
sampling logic.
STATUS & MODE REGISTER
The HI-1575 is configured by writing bits 0 - 5 of the Sta-
tus & Mode (SAM) register. Refer to figure 2 for a com-
plete description. SAM bits 0 - 5 are read/write allowing
the user to verify the chip's configuration at any time by
reading the SAM. SAM is accessed by performing a read
or write cycle with the REG input high.
SAM bits 6 - 15 are read-only and are used to provide
status information.
To minimize the number of hardware control inputs, SAM
bit 5 (Channel A/B select) is logically 'OR'ed with the
CHA/CHB input pin. To select between MIL-STD-1553
bus A or B, the user may either tie the CHA/CHB pin low
and select buses using SAM bit 5 (software control), or
program SAM bit 5 to a zero and use the CHA/CHB pin
to select the active bus (hardware control).
Similarly, the SYNC I/O pin may be left open-circuit al-
lowing the transmitter sync to be programmed into SAM
bit 4, or SAM bit 4 can be set to zero and the SYNC pin
used to set the transmitted SYNC type. Note that SYNC
is an I/O pin. It is an input when writing data to the
HI-1575 transmit data register (TX), and an output when
reading data from the HI-1575 receivers (RXA and RXB).
The SYNC pin must not be shorted directly to VDD or
GND. An internal pull-down resistor allow the SYNC pin
to be left open-circuit if the user opts for purely software
control.
TRANSMITTER
Data words to be transmitted on the MIL-STD-1553 data
bus are written to the TX register by pulsing STRB low
while R/W is low and REG is low. The logical OR of the
CHA/CHB input pin and SAM bit 5 (CHAN) during the
write cycle determines whether the word is output on
MIL-STD-1553 bus A or B. Setting CHA/CHB OR CHAN
to a zero selects bus A, and a one selects bus B. The log-
ical OR of the SYNC pin and SAM bit 4 (TXSYNC) dur-
ing the write cycle defines whether the transmitted word
is a MIL-STD-1553 Command or Data word. Setting
SYNC to a one causes a Command (or Status) sync to
be generated. Setting SYNC to zero selects a Data sync.
Note that the SYNC pin is bidirectional. It should be
treated as an extension to the 16-bit bidirectional
databus (D15:D0) in terms of I/O switching and timing.
The HI-1575 automatically calculates and appends the cor-
rect parity bit to the transmitted word. Each word is as-
signed odd parity as required by MIL-STD-1553.
HOLT INTEGRATED CIRCUITS
2
HI-1575
4
30
CLK
STRB
R/W
REG
MR
10
9
8
11
Encoder
2
BUSA
3
BUSA
VDD
SHIFT
TX
CHA/CHB
31
5
6
BUSB
BUSB
DATABUS
SYNC
RCVA
12
1
SHIFT
RXA
13-20,
22-29
Decoder A
SHIFT
RXB
Decoder B
RCVB
7
6
10
32
ERROR
STATUS & MODE
21
GND
Note: Pin numbers reflect QFP package
FIGURE 1. HI-1575 BLOCK DIAGRAM
To transmit contiguous words, a second write to the TX
register must occur no earlier than 3.5 µs and no later
than 18.5 µs after the first TX write. SAM bit 15
(SENDDATA) is high during this period and may be used
as a flag to indicate when the HI-1575 is ready to accept
the next data write for contiguous transmission. When
transmitting a message of three or more words, the third
and subsequent write operations should occur every 20.0
us so as to avoid over-writing the previous data before it is
transferred to the transmitter's shift register.
Figure 3 shows a timing diagram for transmit operations.
The transmitter outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus. Both coupling
methods produce a nominal voltage on the main
MIL-STD-1553 bus of 7.5 volts peak-to-peak, line-to-line.
Figure 6 shows bus coupling examples.
One or both transmitters may be disabled by writing a '1'
into SAM register bits 0 or 1 (TXDISA, TXDISB). When dis-
abled, the host interface works as normal, but there is no
output from the BUSA and BUSA (BUSB and BUSB) pins.
RECEIVER
The HI-1575's two receivers continuously monitor both
MIL-STD-1553 data busses. Bi-phase differential data
words are accepted from the MIL-STD-1553 bus through
the same direct or transformer coupled interface as the
transmitter. Each receiver’s differential input stage drives
a filter and threshold comparator that presents data to the
decoders.
The decoder logic checks the incoming word for correct
encoding, bit count and parity. If a valid MIL-STD-1553
word is received, the RCVA or RCVB output goes high
and the 16-bit received word is transferred to the RXA or
RXB register. The HI-1575 ERROR output goes high
whenever an encoding error is detected on either bus. If
a received word has an encoding error, then SAM bits 10
or 14 (ERRORA, ERRORB) are set high, and the
corresponding RCVA or RCVB pin is not asserted.
To minimize the number of pins necessary to interface the
HI-1575, the state of RCVA and RCVB can also be read
from SAM bits 7 and 11.
HOLT INTEGRATED CIRCUITS
3
HI-1575
STATUS & MODE REGISTER (SAM)
15 14 13 12 11 10 9
MSB
8
7
Bit Name
0
1
2
3
4
TXDISA
TXDISB
RENA
RENB
TXSYNC
R/W
R/W
R/W
R/W
R/W
R/W
Default Description
0
0
1
1
0
Writing TXDISA to a '1' disables the transmitter for MIL-STD-1553 bus A
Writing TXDISB to a '1' disables the transmitter for MIL-STD-1553 bus B
Setting RENA to a '1' enables the receiver for MIL-STD-1553 bus A. A '0' disables the
receiver causing the HI-1575 to ignore all activity on bus A.
Setting RENB to a '1' enables the receiver for MIL-STD-1553 bus B. A '0' disables the
receiver causing the HI-1575 to ignore all activity on bus B.
The TXSYNC bit is logically ORed with the SYNC input pin during host write cycles to the
Transmit Data Register (TX). If TXSYNC OR SYNC is a '1' the transmitter prefixes the
transmitted word with a MIL-STD-1553 Command Sync. If TXSYNC OR SYNC is a '0'
during a write to TX, then the transmitted word has a MIL-STD-1553 Data Sync.
The CHAN bit is logically ORed with the CHA/CHB input pin and the result used to Select
between MIL-STD-1553 bus A or B during write transfers to the TX register, or reading data
from the RX registers. When CHAN OR CHA/CHB is a '0' during a transmit operation,
data is transmitted on MIL-STD-1553 bus A. When the result is a '1', MIL-STD-1553
bus B is selected. During HI-1575 data read cycles, if CHAN OR CHA/CHB is a '0', the RXA
register is accessed, and if CHAN OR CHA/CHB is a '1' then the data is read from RXB.
Not used. Internally set to '0'.
This bit reflects the state of the RCVA output pin. RCVA goes high whenever a new word is
received on MIL-STD-1553 bus A. The received word may be read by the host from the RXA
register. RCVA is reset on reading RXA or if the HI-1575 detects a new word arriving on bus A.
If the data words are contiguous, then RCVA will be high for about 3 us before the new word
resets it. The data is still available in the RXA register and may be retreived any time up until
the RCVA flag goes high again. If the user does not read the data, the word is lost when
the RCVA flag goes high on reception of the next word.
RSYNCA indicates the Sync of the last MIL-STD-1553 word received on bus A. RSYNCA is a
'0' for a Data sync, and a '1' for a Command Sync. When the RXA register is read, the
RSYNCA value is also output on the SYNC I/O pin.
GAPA is a '1' when there is no activity detected on MIL-STD-1553 bus A, for example during an
inter-message gap. GAPA is a '0' whenever the HI-1575 detects bus traffic.
ERRORA goes high when the HI-1575 Manchester decoder receives an incorrectly encoded
word on MIL-STD-1553 bus A
Same function as RCVA but for MIL-STD-1553 bus B.
Same function as RSYNCA but for MIL-STD-1553 bus B.
Same function as GAPA but for MIL-STD-1553 bus B.
Same function as ERRORA but for MIL-STD-1553 bus B.
SENDDATA goes high approximately 3.5 us after the start of a MIL-STD-1553 word
transmission. SENDATA goes low approximately 18.5 us after the start of a MIL-STD-1553
word transmission. If new a new data word is written to the TX register while SENDDATA is
high, that word will be transmitted contiguously after the currently transmitting word.
5
CHAN
R/W
0
6
7
-
RCVA
Read-only
Read-only
0
0
8
RSYNCA
Read-only
0
9
GAPA
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
0
0
0
0
0
0
1
10 ERRORA
11
RCVB
12 RSYNCB
13 GAPB
14 ERRORB
15 SENDDATA Read-only
FIGURE 2. STATUS AND MODE REGISTER
HOLT INTEGRATED CIRCUITS
4
SE
N
ER DD
R AT
G OR A
AP B
R B
SY
R NC
C B
V
ER B
R
G OR
AP A
R A
SY
R NC
C A
V
N A
ot
u
C se
H d
A
TX N
S
R YN
EN C
R B
EN
TX A
D
TX ISB
D
IS
A
0
6
5
4
3
2
1
0
LSB
HI-1575
Write TX,
(MIL-STD-1553 Status word)
Write TX,
(MIL-STD-1553 Data word)
Read SAM,
check SENDDATA=1
D15 - D0
TXDATA
DON’T CARE
SAM
TXDATA
R/W
DON’T CARE
CHA/CHB
VALID
DON’T CARE
VALID
SYNC
DON’T CARE
REG
DON’T CARE
STRB
BUSA (B)
SYNC
SYNC
15
14
13
3
3
2
1
0
P
SYNC
SYNC
15
FIGURE 3. EXAMPLE TRANSMIT OPERATION
Read RXA or RXB,
(MIL-STD-1553 Data word)
Read SAM
BUSA (B)
SYNC
SYNC
15
14
13
12
2
1
0
P
SYNC
SYNC
15
14
13
12
RCVA (B)
R/W
DON’T CARE
CHA/CHB
DON’T CARE
VALID
REG
DON’T CARE
STRB
D15 - D0
SAM
RXA (B)
SYNC
SYNC
FIGURE 4. EXAMPLE RECEIVE OPERATION
CHAN OR CHA/CHB
0
1
X
REG
0
0
1
Register
Receiver A Data (RXA)
Receiver B Data (RXB)
Status & Mode Register (SAM)
FIGURE 5. HI-1575 REGISTER MAP
HOLT INTEGRATED CIRCUITS
5
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