DATASHEET
HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
CMOS Analog Switches
This family of CMOS analog switches offers low resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
operating signal voltage and current. r
ON
remains
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
0
o
C and 75
o
C. r
ON
is nominally 25 for HI-5049 and
HI-5051 and 50 for HI-5042 through HI-5047.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at 25
o
C).
This family of switches also features very low power
operation (1.5mW at 25
o
C).
There are 7 devices in this switch series which are
differentiated by type of switch action and value of r
ON
(see
Functional Description Table). The HI-504X and HI-505X series
switches can directly replace IH-5040 series devices, and are
functionally compatible with the DG180 and DG190 family
FN3127
Rev 7.00
June 16, 2016
Features
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . .
15V
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 25
• High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA
• Break-Before-Make Switching
- Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns
- Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns
• No Latch-Up
• Input MOS Gates are Protected from Electrostatic
Discharge
• DTL, TTL, CMOS, PMOS Compatible
• Pb-Free Available (RoHS Compliant)
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
S
A
N
P
D
Functional Description
PART NUMBER
HI-5042
HI-5043
HI-5047
HI-5049
HI-5051
SPDT
Dual SPDT
4PST
Dual DPST
Dual SPDT
TYPE
r
ON
50
50
50
25
25
FN3127 Rev 7.00
June 16, 2016
Page 1 of 13
HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
Ordering Information
PART NUMBER
HI1-5042-2
HI1-5043-2
HI1-5043-5
HI3-5043-5
HI3-5043-5Z
(See Note)
HI9P5043-5
HI9P5043-5Z
(See Note)
HI1-5047-5
HI1-5049-5
HI1-5051-2
HI1-5051-5
HI3-5051-5
HI3-5051-5Z
(No longer available, recommended
replacement: HI9P5051-9Z
(See Note)
HI9P5051-9
HI9P5051-9Z
(See Note)
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
-55 to 125
0 to 75
0 to 75
0 to 75
-40 to 85
-40 to 85
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP*
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP *
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
PKG. DWG. #
F16.3
F16.3
F16.3
E16.3
F16.3
M16.15
M16.15
F16.3
F16.3
F16.3
F16.3
E16.3
E16.3
M16.15
M16.15
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
(SWITCHES SHOWN FOR LOGIC “0” INPUT)
Pinouts
(SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
SPDT
HI-5042 (50)
D
1
1
2
D
2
3
S
2
4
5
6
7
8
16 S
1
15 A
14 V-
13 V
R
12 V
L
11 V+
10
9
D
2
1
2
D
1
3
S
1
4
S
4
5
D
4
6
7
D
3
8
Dual Control
4PST
HI-5047 (50)
16 S
2
15 A
14 V-
13 V
R
12 V
L
11 V+
10
9 S
3
DUAL SPDT
HI-5043 (50), HI-5051 (25)
D
1
1
2
D
3
3
S
3
4
S
4
5
D
4
6
7
D
2
8
16 S
1
15 A
1
14 V-
13 V
R
12 V
L
11 V+
10 A
2
9 S
2
D
1
1
2
D
3
3
S
3
4
S
4
5
D
4
6
7
D
2
8
DUAL DPST
HI-5049 (25)
16 S
1
15 A
1
14 V-
13 V
R
12 V
L
11 V+
10 A
2
9 S
2
NOTE: Unused pins may be internally connected. Ground all
unused pins.
NOTE: Unused pins may be internally connected. Ground all
unused pins.
FN3127 Rev 7.00
June 16, 2016
Page 2 of 13
HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
Switch Functions
(SWITCHES SHOWN FOR LOGIC “1” INPUT)
DUAL SPDT
HI-5043 (50)
V
L
12
1
3
D
1
D
2
S
1
S
3
A
1
A
2
S
2
S
4
16
4
15
10
9
5
13
V
R
14
V-
V+
11
1
3
D
1
D
3
SPDT
HI-5042 (50)
V
L
12
S
1
S
2
A
16
4
15
V+
11
8
6
D
2
D
4
13
V
R
14
V-
4PST
HI-5047 (50)
V
L
12
S
1
S
2
S
3
S
4
A
4
16
9
5
15
V+
11
3
1
8
6
D
1
D
2
D
3
D
4
S
1
S
3
A
1
A
2
S
2
S
4
13
V
R
14
V-
16
4
15
10
9
5
DUAL DPST
HI-5049 (25)
V
L
12
V+
11
1
3
D
1
D
3
S
1
S
3
A
1
8
6
13
V
R
14
V-
D
2
D
4
A
2
S
2
S
4
16
4
15
10
9
5
DUAL SPDT
HI-5051 (25)
V
L
12
V+
11
1
3
D
1
D
3
8
6
13
V
R
14
V-
D
2
D
4
FN3127 Rev 7.00
June 16, 2016
Page 3 of 13
HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
Schematic Diagrams
V
L
35A
R6
QP4
R3
N13
100A
25A
25A
QP1
25A
P15
P14
QN1
P16
V+
QP3
QP5
QP8
R2
V
R
QP6
R4
P13
25A
QP7
25A
R5
16A
V+
TO V
R
’
R7
QN2
QP2
V-
N16
to V
L
’
N14
N15
NOTE: Connect V+ to V
L
for minimizing power consumption when driving from CMOS circuits.
TTL/CMOS REFERENCE CIRCUIT
(NOTE)
A
1
(A
2
)
N1
V+
IN
P2
V-
P1
N3
N2
OUT
A
1
(A
2
)
SWITCH CELL
V+
P3
P5
P4
P6
P7
P8
P9
P10
P11
P12
A1
A1
A2
A2
N6
V-
P2
N4
N2
N5
N3
V-
N7
N8
N9
N10
N11
N12
V+
P1
N1
D1
R4
A
200
D2
V
R
'
V
L
'
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
FN3127 Rev 7.00
June 16, 2016
Page 4 of 13
HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
V
R
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+, V-
Digital and Analog Input Voltage . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Current (S to D) Continuous . . . . . . . . . . . . . . . . . . . . 30mA
Analog Current (S to D) Peak . . . . . . . . . . . . . . . . . . . . . . . . . 80mA
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
75
22
SOIC Package . . . . . . . . . . . . . . . . . . .
110
N/A
PDIP Package* . . . . . . . . . . . . . . . . . .
90
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
o
C
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
HI-50XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; V
R
= 0V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = 0.8V, V
L
= 5V,
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded
TEST
CONDITIONS
TEMP
(
o
C)
-2
MIN
TYP
MAX
MIN
-5, -9
TYP
MAX
UNITS
PARAMETER
DYNAMIC CHARACTERISTICS
Switch ON Time, t
ON
Switch OFF Time, t
OFF
Charge Injection, Q
OFF Isolation
Crosstalk
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance, C
D(OFF)
Output Switch Capacitance, C
D(ON)
Digital Input Capacitance, C
A
Drain To Source Capacitance, C
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
AL
Input High Threshold, V
AH
Input Leakage Current (High or Low), I
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
ON Resistance, r
ON
HI-5042 to HI-5047
(Note 5)
(Note 5)
(Note 3)
(Note 4)
(Note 4)
25
25
25
25
25
25
25
25
25
25
-
-
-
75
-80
-
-
-
-
-
370
280
5
80
-88
11
11
22
5
0.5
500
500
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
370
280
5
80
-88
11
11
22
5
0.5
500
500
-
-
-
-
-
-
-
-
ns
ns
mV
dB
dB
pF
pF
pF
pF
pF
Full
Full
Full
-
2.4
-
-
-
0.01
0.8
-
1.0
-
2.4
-
-
-
0.01
0.8
-
1.0
V
V
A
Full
(Note 2)
25
Full
-15
-
-
-
-
-
-
-
50
-
25
-
2
1
+15
75
150
45
50
10
5
-15
-
-
-
-
-
-
-
50
-
25
-
2
1
+15
75
150
45
50
10
5
V
HI-5049, HI-5051
(Note 2)
25
Full
Channel-to-Channel Match,
r
ON
HI-5042 to HI-5047
HI-5049, HI-5051
25
25
FN3127 Rev 7.00
June 16, 2016
Page 5 of 13
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