HI-6110
September 2013
MIL-STD-1553
BC / RT / MT Message Processor
FEATURES
Monolithic CMOS Technology
3.3V operation
Exceptionally low power
On-chip message buffering
Selectable master clock frequency
Dual differential 1553 bus transceivers
Bus Controller / Remote Terminal /
Monitor Terminal operating modes
• Compliant to MIL-STD-1553B Notice 2
•
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•
•
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GENERAL DESCRIPTION
The HI-6110 is a CMOS integrated circuit implementing the
MIL-STD-1553 (1553) data communications protocol
between a host processor and a dual redundant 1553 data
bus. The single chip architecture has a digital section
containing all necessary logic and memory to process and
store the command and data words for one complete 1553
message. The analog section includes dual transceivers
coupled to the 1553 buses through external current mode
transformers. The device is available in an industry standard
64-pin 9 mm square QFN package, making it the smallest
dual redundant 1553 interface product on the market.
The HI-6110 may be configured as a Bus Controller (BC), a
Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor
Terminal with assigned RT address. 16-bit registers store
incoming and outgoing Command, Status and Data words.
Using two 32-word data FIFOs, the HI-6110 can store the
maximum number of 1553 words occurring in any message.
For messages with transmitted data words, data may be
written in advance or on-the-fly. Received data can be
retrieved on-the-fly or all at once after the Valid Message flag
is asserted.
BC message sequences are initiated by a rising edge on the
BCSTART input, or a 0 to 1 transition at the BCSTART bit in
the Control Register. All RT command responses are
automatically initiated after a valid Command Word is
received.
A single encoder services both buses, each of which have a
dedicated analog transformer driver. Each driver dissipates
less than 200 mW of on-chip power at 100% duty cycle.
Each bus receiver has a dedicated Manchester decoder. In
BC mode, a RCV signal indicates when valid 1553 words are
received. In RT/MT modes, RCV indicates a valid command
received, while the 1553 command decoder updates a
Message register so the external controller can identify
command type and respond appropriately. Guaranteed by
design, the HI-6110 cannot generate messages exceeding
660uS, the duration of a Command or Status Word plus 32
contiguous data words.
The external host controller reads and writes a simplified
register structure in the HI-6110 over a 16-bit parallel bus.
The system designer has flexibility over many aspects of
configuration. Control and status monitoring can be done in
hardware (by reading/writing control pins) or in software (by
reading/writing register bits).
APPLICATIONS
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MIL-STD-1553 Terminals
Flight Control and Monitoring
ECCM Interfaces
Stores Management
Test Equipment
Sensor Interfaces
Instrumentation
52 - STR
51 - VDDLOG
50 - RTAP
49 - RTA4
48 - RTA3
47 - RTA2
46 - RTA1
45 - RTA0
44 - RTMODE
43 - BCMODE
42 - RCVA
41 - TXINHA
40 - BUSA
PIN CONFIGURATION
(Top View)
R/W - 1
CS - 2
D0 - 3
D1 - 4
D2 - 5
D3 - 6
D4 - 7
D5 - 8
D6 - 9
D7 - 10
D8 - 11
D9 - 12
D10 - 13
HI-6110PQI
&
HI-6110PQT
39 - VDDA
38 - BUSA
37 - BUSB
36 - VDDB
35 - BUSB
34 - TXINHB
33 - RCVB
32 - FFEMPTY
31 - RF0 / RCMDA
30 - RF1 / RCMDB
29 - RFLAG
28 - VALMESS
27 - ERROR
52 Pin Plastic Quad Flat Pack (PQFP)
See page 35 for 64-Pin QFN Pin Configuration
(
(DS6110 Rev. S)
HOLT INTEGRATED CIRCUITS
www.holtic.com
D11 - 14
D12 - 15
D13 - 16
D14 - 17
D15 - 18
RA2 - 19
RA1 - 20
RA0 - 21
BCSTART - 22
RA3 - 23
CLK - 24
GND - 25
MR - 26
09/13
HI-6110
PIN DESCRIPTIONS
SIGNAL
STR
R/W
CS
D0 - D15
RA0 - RA3
BCSTART
FUNCTION
INPUT
INPUT
INPUT
I/O
INPUTS
INPUT
DESCRIPTION
During I/O operations, data is latched on rising edge. (Internal 12K
W
pull-up)
Device register access, READ = 1, WRITE = 0. (Internal 12K
W
pull-up)
Chip Select for register reads and writes, active low. (Internal 12K
W
pull-down)
Data bus signals. (Internal 12K
W
pull-down per signal)
Register access address, inputs are ORed with corresponding Control register bits.
(Internal 12K
W
pull-down per signal)
Message starts on rising edge when in BC mode. Input is ORed with a corresponding
Control register bit, where a 0 to 1 transition will also trigger message start. (This input
has an Internal 12K
W
pull-down.)
System Clock. (Internal 12K
W
pull-down)
Power supply Ground, 0V.
Master Reset, active high. Clears all data FIFOs and all registers except the Control,
Transmit Status Word and Transmit Mode Data Word registers. This input is ORed
with a corresponding Control register bit. (Internal 12K
W
pull-down)
ERROR goes high when a message error is detected.
In BC mode, ERROR resets when BCSTART is asserted to begin the next message.
For RT and MT modes, ERROR resets automatically after 3 to 4uS.
This output signal mirrors a corresponding Status register bit.
Goes high at the end of a valid message sequence. This output signal mirrors a
corresponding Status register bit.
When low, data is available in the receive data FIFO for the active bus. This output
signal mirrors a corresponding Status register bit.
This pin goes low each time the decoder detects a valid 1553 word on the active data
bus, set by Control Register bits 5:4. Falling edges occur for command words, status
words and mode command data words, but not for data words associated with
subaddress commands. Signal is not asserted for words on the inactive bus, or for
words transmitted by the device itself, e.g., no assertion for command words when in
BC mode. Use falling edge-triggered logic only; Falling edge typically occurs 3us after
the detected word's mid-parity. This output mirrors a corresponding Status register bit.
RF0 function: If “1” when reading Bus A Word register, the stored word had data sync.
RCMDA function: In RT or MT mode, pin goes high when a valid receive command
was decoded on Bus A. This output mirrors a corresponding Status register bit.
RF1 function: If “1” when reading Bus B Word register, the stored word had data sync.
RCMDA function: In RT or MT mode, pin goes high when a valid receive command
was decoded on Bus B. This output mirrors a corresponding Status register bit.
Receive A and Receive B flags: In BC mode, these signals go high when any valid
word is received on Bus A or Bus B.
In RT or MT mode, these signals go high when a valid command is received on Bus A
or Bus B. For valid RT-to-RT only, RCV goes high after command word pair. These
output signals mirror two corresponding Status register bits.
Logic one disables the Bus A transmitter. (Internal 12K
W
pull-up)
Logic one disables the Bus B transmitter. (Internal 12K
W
pull-up)
Positive and negative polarity of 1553 signals for Buses A and B. These signal pairs
connect the analog transceivers to the external transformer.
Selects operating mode. This input signal is ORed with a corresponding
Control register bit. (Internal 12K
W
pull-up)
Selects operating mode. This input signal is ORed with a corresponding
Control register bit. (Internal 12K
W
pull-down)
Remote Terminal address inputs, for RT mode. (Internal 12K
W
pull-up per signal)
This input sets Remote Terminal address parity, odd. (Internal 12K
W
pull-down)
+3.3VDC ±5% power supply input for internal logic
+3.3VDC ±5% power supply inputs for Bus A and Bus B transceivers
CLK
GND
MR
INPUT
POWER
INPUT
ERROR
OUTPUT
VALMESS
FFEMPTY
RFLAG
OUTPUT
OUTPUT
OUTPUT
RF0 /
RCMDA
RF1 /
RCMDB
RCVA
RCVB
OUTPUT
OUTPUT
OUTPUTS
TXINHA
TXINHB
BUSA, BUSA
BUSB, BUSB
BCMODE
RTMODE
INPUT
INPUT
XFMR
INPUT
INPUT
RTA0-RTA4
INPUTS
RTAP
INPUT
VDDLOG
POWER
VDDA, VDDB POWER
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HI-6110
FUNCTIONAL DESCRIPTION
HOST INTERFACE
The Holt HI-6110 provides a simple interface between a host
subsystem and a MIL-STD-1553 dual redundant data bus.
Messages are processed one at a time. The HI-6110 automatically
handles message formatting, error checking, message data
buffering, protocol checking and default responses. The host may
override default message responses by updating registers on-the-
fly.
The host communicates with the HI-6110 using a 16-bit
bidirectional data bus. On-chip bus transceivers allow the device to
be connected to the MIL-STD-1553 data buses using external
coupling transformers.
The HI-6110 can be configured as 1553 Bus Controller (BC),
Remote Terminal (RT) or Bus Monitor (MT). The BCMODE and
RTMODE inputs define the mode of operation as follows:
BCMODE RTMODE 1553 OPERATING MODE
1
0
Bus Controller (BC)
0
1
Remote Terminal (RT)
1
1
Bus Monitor (no assigned RT address)
0
0
Bus Monitor with assigned RT address
The HI-6110 is further configured by setting various configuration
bits in the on-chip Control Register. Different sets of 16-bit registers
and message data FIFOs are available depending upon the mode
of operation (BC, RT or MT). The STR pin is used as the timing
signal for data read and write cycles. Data is output on the 16-bit
bidirectional data bus, D15-D0, when R/W is high and STR is low.
D15-D0 are inputs when R/W is low, and data is written into internal
registers on the rising edge of the STR signal. The Chip Select input
CS must be low for all register read / write operations:
CS R/W STR
1
X
X
0
X
1
0
1
0
0
0
0
D15-D0
High impedance
High impedance
Output
Input
OPERATION
No operation
No operation
Read
Write (on STR rising edge)
Four Register address inputs (RA3, RA2, RA1, RA0) are used to
select internal registers during host read or write operations. Note
that internal registers may be write-only, read-only or read/write.
The register address map is different for BC, RT and MT modes as
not all registers are used in each mode. Table 1 defines the HI-6110
address map in detail.
Table 1. HI-6110 Internal Register Address Map
ADDRESS
RA3:0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
REGISTER READ (R/W=1)
MODE
BC
RT or MT with assigned RT address
STATUS WORD 1 ( if RT-RT, Receive RT ) COMMAND WORD 1
STATUS WORD 2 only RT-RT Transmit RT COMMAND WORD 2 (from last RT-RT)
-
RECEIVED MODE DATA WORD
-
RECEIVED STATUS WORD (from last RT-RT)
RECEIVED DATA FIFO
RECEIVED DATA FIFO
STATUS REGISTER
STATUS REGISTER
-
MESSAGE REGISTER
ERROR REGISTER
ERROR REGISTER
-
-
BUS A WORD
BUS A WORD
BUS B WORD
BUS B WORD
CONTROL REGISTER
CONTROL REGISTER
REGISTER WRITE (R/W=0)
MODE
RT or MT with assigned RT address
TRANSMIT STATUS WORD
TRANSMIT MODE DATA WORD
RESET TRANSMIT DATA FIFO
TRANSMIT DATA FIFO
CONTROL REGISTER
MT without assigned RT address
COMMAND WORD 1
COMMAND WORD 2 from last RT-RT
BC-transmitted MODE DATA WORD
Transmit RT STATUS WORD from last RT-RT
DATA FIFO, incl. RT-transmitted mode data
STATUS REGISTER
MESSAGE REGISTER
ERROR REGISTER
STATUS WORD (from receiving RT, if RT-RT)
BUS A WORD
BUS B WORD
CONTROL REGISTER
ADDRESS
RA3:0
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 1
X 1 X X
BC
COMMAND WORD 1
COMMAND WORD 2 ( used for RT-RT only)
TRANSMIT DATA FIFO
-
CONTROL REGISTER
MT without assigned RT address
-
-
-
CONTROL REGISTER
Table 2. MIL-STD-1553 Word Type Decoding
SIGNAL
RF1 RF0
0 0
0 1
1 0
SIGNALS RF1 AND RF0 IDENTIFY LAST RECEIVED 1553 WORD TYPE
MODE
BC
RT or MT with assigned RT address
MT without assigned RT address
-
-
-
pulses low if STATUS WORD 2
Valid Receive Command Bus A
Valid Receive Command Bus A
-
Valid Receive Command Bus B
Valid Receive Command Bus B
While reading the BUS A WORD or BUS B WORD registers, sync type for the stored word can be determined from the RF0 and RF1 outputs.
While the /STR input is held low, output RF1 = 1 if the stored Bus Word had Command Sync, or output RF0 = 1 if the stored Bus Word had Data Sync.
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HI-6110 (BUS CONTROLLER MODE)
BUS CONTROLLER
The HI-6110 is configured for Bus Controller operation by setting
the BCMODE input high and the RTMODE input low. Alternatively,
Control Register bits 3:2 (RTMODE:BCMODE) may be
programmed to 0:1. Control Register bits 3:2 are logically ORed
with the input pins with the same signal name.
Figure 1. shows a block diagram of the HI-6110 in Bus Controller
mode
INITIALIZATION
In Bus Controller mode, the user must first perform a Master Reset
to initialize the BC protocol engine and clear all message registers
and data FIFOs. This may be achieved by pulsing the MR input
high, or writing a "1" to Control Register bit 0. The user must select a
master clock (CLK) frequency by programming Control Register
bits 11 and 12, and the Response Time Out must be programmed
per Control Register bit 14. Refer to the BC Register Formats
section for a full description of available registers and their
functions in Bus Controller Mode.
Command Word 1
Command Word 2
Parallel
to
Serial
Manchester
Encoder
TXINHA
TX
DATA
FIFO
BUSA
Serial
to
Parallel
Bus A
Manchester
Decoder
BUSA
Transceiver
Bus A Word
D15-D0
CS
R/W
STR
RA2-RA0
FFEMPTY
Host
Data
Interface
Status Word 1
Status Word 2
Mux
RX
DATA
FIFO
TXINHB
Bus B Word
BUSB
Serial
to
Parallel
Bus B
Manchester
Decoder
BUSB
Transceiver
VALMESS
ERROR
RFLAG
RCVA
RCVB
RF0
RF1
Status Register
Message
Status
Control Register
BC Error Register
CLK
MR
BCSTART
BCMODE
RTMODE
Protocol
Control
BC Protocol Engine
Figure 1. Block Diagram - Bus Controller Mode
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HI-6110 (BUS CONTROLLER MODE)
REGISTER FORMATS (BC Mode)
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
A
RT
M
BC O D
M E
BC OD
S E
M TA
R RT
ot
R U se
EP d
N TO
ot
U
C
se
LK
d
R
SE
es
L
e
R rv e
A3 d
R
A2
R
A1
R
A0
X
X
0
8
7
X
6
5
4
0
3
1
2
1
0
LSB
MSB 15 14 13 12 11 10 9
The Control Register settings determine HI-6110 operating
mode, clock frequency and the bus enabled for transmit. It can
also be used to address registers for read/write operations, to
assert master reset, and to initiate MIL-STD-1553 message
sequences.
TR
BIT
15
14
NAME
-
REPTO
13
12
-
CLKSEL
11
10 - 7
Reserved
RA3:0
6
5-4
-
TRB, TRA
3-2
RTMODE,
BCMODE
1
0
BCSTART
MR
FUNCTION
Not used in BC mode
Controls the time-out which causes the No Response Error.
0
17 usec Gap (equivalent to 57 usec for 5.2.1.7 of the RT Validation Test Plan)
1
131 usec Gap
Not used in BC mode
Selects the frequency of the HI-6110 external CLK input, as follows:
CLKSEL
Value
0
24 MHz
1
12 MHz
This bit must be written to “0”.
Register Address for HI-6110 register and data read and write operations. The register address is defined by
the logical OR of these bits and their corresponding input pins. Writting Control Register bits 10:7 to 0000 is
necessary if the RA0 - RA3 input pins are used for HI-6110 register addressing.
Not used in BC mode
Setting either TRA or TRB to "1" enables transmit on MIL-STD-1553 BUS A or BUS B. Setting both TRA and
TRB selects neither bus. The BC protocol engine connects to the selected, active bus. The 1553 receiver,
Manchester decoder and RCV output signal are still operational on the inactive bus. Valid words received on the
inactive bus can be read without changing active bus by reading the Bus A Word or Bus B Word register.
NOTE: The TXINHA and TXINHB input pins can override bus enablement.
HI-6110 mode select bits. These Control Register bits are logically OR'ed with their corresponding input pins,
allowing the user to select 1553 operating mode under either hardware or software control:
RTMODE BCMODE
1553 OPERATING MODE
0
0
Bus Monitor (MT), with assigned RT address
0
1
Bus Controller (BC)
1
0
Remote Terminal (RT)
1
1
Bus Monitor (MT), without assigned RT address
If initially reset, writing a "1" to this bit initiates a BC message sequence. This bit should be reset before next
message.
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affected by Master Reset.
TRANSMIT DATA FIFO (Write only) Write Address: X010
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10 9
MSB
8
7
6
5
4
3
2
1
0
LSB
TR
N
B
The Transmit Data FIFO is 32-words deep and holds MIL-
STD-1553 message data. The FIFO is cleared on Master
Reset.
Message data to be transmitted by the BC may be loaded into
the TRANSMIT DATA FIFO by the host prior to BCSTART.
Any data word must be loaded before mid-parity bit for the
1553 word it follows. Words are transmitted in the order they
are loaded.
The Receive Data FIFO is 32-words deep and holds MIL-
STD-1553 message data. The FIFO is cleared by Master
Reset or when BCSTART occurs.
RECEIVE DATA FIFO (Read only) Read Address: 0100
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10 9
MSB
8
7
6
5
4
3
2
1
0
LSB
All MIL-STD-1553 data words received by the BC are stored in
the Receive DATA FIFO. A low FFEMPTY flag (output pin or
Status register bit) means message data is available to be
read by the host. Successive data reads cause FFEMPTY to
go high when the last word is read.
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