HI-8050/51, HI-8150/51
February 2003
CMOS HIGH VOLTAGE DISPLAY DRIVER
APPLICATIONS
!
!
!
!
Dichroic Liquid Crystal Displays
Standard Liquid Crystal Displays
5 Volt Serial Data to Parallel High Voltage
MEMS Drivers
GENERAL DESCRIPTION
The HI-8050, HI-8051, HI-8150 and HI-8151 are CMOS
integrated circuits designed for high voltage LCD display
drive applications. The HI-8050 & HI-8051 have TTL logic
inputs whereas the HI-8150 & HI-8151 have CMOS logic
inputs. They drive up to 38 segments at voltages between
+5 and -30 volts. The optional voltage converter on the
HI-8050 & HI-8150 can be used to generate the negative
display drive voltage. All products have test inputs to
facilitate opens and shorts testing as well as automatic
blanking of the display if the +5V power is lost.
The HI-8050 and HI-8150 are designed to replace the
HI-8010 and HI-8020 devices in all 5 volt applications. They
offer significantly enhanced ESD protection along with a
considerably faster serial input data rate.
The data is serially clocked into the device on the negative
edge of the clock and latched in parallel to the segment
outputs on the high to low transition of the load input. Serial
output data changes on the positive edge of the clock
allowing the cascading of multiple drivers for larger dis-
plays.
The device layout supports all previous pinouts of the
HI-8010/HI-8020 products. In addition, new technology
and features afford new packaging options. Consult your
Holt Sales Representative to explore the possibilities.
PAD CONFIGURATION
(Top View)
N/C
DIN
LD
CL
CS
8020OPT
VSS
S36
S35
S34
S33
S32
S31
S30
S29
S28
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
(See page 6 for HI-8051 & HI-8151pin configurations)
FEATURES
!
4 MHz serial input data rate
!
38 segment outputs
!
Cascadable
!
5 Volt inputs translated to 35 Volts
!
Test pins allow hardware all "ON", all "OFF" or
alternating
!
Monitors 5 volt supply and forces all
segments to "OFF" condition if lost
!
Negative voltage converter available on-chip
!
CMOS low power
!
Military processing available
H i g h Vo l ta g e
B u ff e r
FUNCTIONAL BLOCK DIAGRAM
DIN
CL
Þ
Þ
CS
Þ
Þ
LD
N/C
S8
S9
S10
S11
S12
S13
S14
N/C
S15
S16
S17
S18
S19
N/C
N/C
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
BPIN
BPOSC
VDD
N/C
CONVOSC
CONVOUT
VEE
S37
S38
S1
S2
S3
S4
S5
S6
S7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HI-8050PQI
HI-8150PQI
HI-8050PQT
&
HI-8150PQT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
S27
S26
S25
S24
S23
S22
S21
S20
DOUT38
DOUT32
DOUT30
T2
T1
N/C
BPOUT
N/C
64 Pin plastic PQFP
DATA IN
3 8 Sta g e
S h i ft R e g i s t e r
CLK
Þ
DOUT38
DOUT32
DOUT30
8020OPT
CONTROL
LOGIC
LE
Þ
BPIN
Þ
BPOSC
Þ
38 Bit Latch
Oscillator
Divider
Vo l ta g e
Tr a n s l a t o r
Vo l ta g e
Tr a n s l a t o r s
H i g h Vo l ta g e
Drivers
Þ
BPOUT
(DS8050 Rev. D)
38 SEGMENTS
HOLT INTEGRATED CIRCUITS
www.holtic.com
02/03
HI-8050/51, HI-8150/51
PIN DESCRIPTION TABLE
SIGNAL
VSS
8020OPT
CS
CL
LD
DIN
BPIN
BPOSC
VDD
CONVOSC
CONVOUT
VEE
S1 to S38
BPOUT
T1
T2
DOUT30
DOUT32
DOUT38
FUNCTION
POWER
0 Volts
DESCRIPTION
LOGIC INPUT Open or high logic level selects the HI-8010/HI-8110 CL / CS logic. A low
selects the HI-8020/HI-8120 Logic (HI-8050 & HI-8150 only)
LOGIC INPUT Chip select - Active low
LOGIC INPUT Serial data input clock - Active low
LOGIC INPUT Latches data in shift register to the segment outputs - Active high
LOGIC INPUT Serial input data to the shift register
INPUT
OUTPUT
POWER
INPUT
OUTPUT
POWER
OUTPUT
OUTPUT
Backplane frequency input. Either driven from an external source or connected
to BPOSC and an external resistor and capacitor.
Internal oscillator pin. Connected to BPIN and an external resistor and capacitor
+5V ±5%, Positive voltage of the backplane and segments
Used in conjunction with CONVOUT to generate the negative VEE voltage
on-chip (HI-8050 & HI-8150 only).
Used in conjunction with CONVOSC to generate the negative VEE voltage
on-chip (HI-8050 & HI-8150 only).
Negative voltage of the backplane and segments - between VSS and VDD - 35V
Segment outputs to LCD display
Backplane output to LCD display (See Figure 3 for cascading drivers)
LOGIC INPUT Used in conjunction with T2 to control display mode. Normal mode is logic low.
LOGIC INPUT Used in conjunction with T1 to control display mode. Normal mode is logic low.
OUTPUT
OUTPUT
OUTPUT
Logic output from the 30th bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only).
Logic output from the 32nd bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only).
Logic output from the 38th bit of the shift register. Use for pattern
verification or as the DIN of the next cascaded driver.
HOLT INTEGRATED CIRCUITS
2
HI-8050/51, HI-8150/51
FUNCTIONAL DESCRIPTION
INPUT LOGIC
The data is clocked into a serial shift register from the DIN in-
put on the negative edge of CL while CS is held low. LD is
normally held low and pulsed high only when data from the
shift register is parallel latched to the segment outputs. CS
must be low when LD is pulsed. The latches are transparent
while LD is high. A logic "1" in the shift register causes the
corresponding segment output to be out of phase with the
BP output. All four logic inputs are TTL compatible on the
HI-8050/51and CMOS compatible on the HI-8150/51.
BPOSC and BPIN
The user has the option of creating the backplane frequency
internally or providing a signal from an external source. For
an internal oscillator, BPIN and BPOSC are connected to-
gether and the appropriate R & C combination is applied as
shown in Figure 1. The resulting backplane frequency is ap-
proximately:
f
BP
=
1
. (R = 220K
W
, C = 220pF, f
BP
»
100HZ)
256 RC
The value of the resistor must be greater than 30K
W
.
Alternatively, BPOSC is left open and an external backplane
signal of the desired frequency is applied to the BPIN input.
VEE & NEGATIVE VOLTAGE CONVERTER
VEE can be connected to a negative power supply. Alterna-
tively, the HI-8050 & HI-8150 have the option of generating
the VEE voltage with a built-in -25 volt negative voltage con-
verter (See Figure 2). When not used, the open CONVOSC
pin is detected and all power consuming circuitry is dis-
abled. The converter will survive a short between two seg-
ments and still maintain a VEE voltage of -20V.
T2
0
0
1
1
T1
0
1
0
1
Display Mode
Normal
All Off
All On
Alternating On/Off Segments
DOUT
The DOUT30, DOUT32, and DOUT38 pins are available for
cascading devices to drive more segments (See Figure 3) and
for verifying the integrity of the shift register data. The outputs
can drive 2 TTL loads. They change on the positive edge of
CL.
AUTOMATIC SEGMENTS OFF
A threshold device detects when the 5V supply is below ap-
proximately 1V and forces all the segments and the backplane
to the same level. This feature is used to discharge the VEE
capacitor when the 5V power is switched off, to prolong the life
of the LCD display.
8020OPT
The CL and CS inputs function the same as the HI-8010 and
HI-8110 product (See Figure 5) if this pin is left open or held
high. If held low, the two pins function the same as the HI-8020
and HI-8120 product (See Figure 6). This input is available
only on the HI-8050 (TTL) and HI-8150 (CMOS) products.
TEST INPUTS
The test functions available are:
The test inputs must be tied to the appropriate logic level for
correct circuit operation. Both test inputs are TTL compatible
on the HI-8050/51 and CMOS compatible on the HI-8150/51.
V
DD
68KW
C
R
CONVOSC
OSC
R
SENSE
Control
÷ 256
V
DD
R
BPIN
BPOSC
C
V
SS
TO BACKPLANE
TRANSLATOR
AND DRIVER
Q
IN5818, IN5819
CONVOUT
330µH
V
SS
V
DD
VEE
10µF
V
SS
Figure 1. INTERNAL OSCILLATOR CIRCUIT
Figure 2. OPTIONAL VOLTAGE CONVERTER
HOLT INTEGRATED CIRCUITS
3
HI-8050/51, HI-8150/51
LD
CL
CS
DIN
BPOUT
CS CL LD
DIN
DO
CS CL LD
DIN
DO
CS CL LD
DIN
DO
1M
W
1500pF
1M
W
1µF
1µF
R
V
os
BPIN BPOUT
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
C
BPOSC
1M
W
SEG
n
SEGMENTS
SEGMENTS
BACK
PLANE
1M
W
1µF
1µF
360pF
SEGMENTS
Figure 3. RC OSCILLATOR AND CASCADED
DEVICES
DIN
Þ
CS
Þ
CL
Þ
Figure 4. OFFSET MEASUREMENT
DATA IN
3 8 Sta g e
S h i ft R e g i s t e r
CLK
Þ
DOUT
DIN
Þ
CS
Þ
CL
Þ
DATA IN
3 8 Sta g e
S h i ft R e g i s t e r
CLK
Þ
DOUT
Figure 5. HI-8010/HI-8110 CL & CS LOGIC
(8020OPT = OPEN or HIGH)
Figure 6. HI-8020/HI-8120 CL & CS LOGIC
(8020OPT = LOW)
CL
INPUT
t
CL
DIN
INPUT
VALID
VALID
t
DS
t
DH
CS
INPUT
t
CSS
t
CSH
LD
INPUT
t
LCS
t
LS
t
CSL
t
CDO
DOUT
OUTPUT
VALID
VALID
t
LS
t
LW
VALID
Figure 7. TIMING DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HI-8050/51, HI-8150/51
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V
VDD ..........................0V to 7V
VEE................VDD-35V to 0V
Voltage at any input, except BPIN..-0.3V to VDD+0.3V
Voltage at BPIN input ..............VDD-35V to VDD+0.3V
DC current per input pin .....................................10 mA
Power Dissipation............................................500 mW
Supply Voltage
Operating Temperature Range(Industrial) ....... -40°C to +85°C
(Hi-Temp/Mil) ..... -55°C to +125°C
Storage Temperature ..................................... -65°C to +125°C
Solder Temperature (Leads) ..................... +280°C for 10 sec.
(Package) ........................................ +220°C
Junction Temperature, Tj ... .......................................
£
+175°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V ±5%, VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Operating Voltage
Supply Current:
(Converter Off, f
BP
= 0Hz)
Input Low Voltage, HI-8050/51 only (except BPIN)
Input High Voltage, HI-8050/51 only (except BPIN)
Input Low Voltage, HI-8150/51 only (except BPIN)
Input High Voltage, HI-8150/51 only (except BPIN)
Input Low Voltage, BPIN
Input High Voltage, BPIN
Input Current
(except T1 & T2)
Input Current
(T1 & T2)
Input Capacitance
(Guaranteed, not tested)
Segment Output Impedance
Backplane Output Impedance
Data Out Current:
Source Current
Sink Current
Voltage Converter:
@ No Load
(VDD - VSS = 5V, TA = 25°C)
@ 0.1mA Load
@ 10K
W
Load
Offset Voltage
(Guaranteed, not tested)
VDD
IDD
IEE
VIL
TTL
VIH
TTL
VIL
CMOS
VIH
CMOS
VILX
VIHX
IIN
1
IIN
2
CI
RSEG
RBP
IDOH
IDOL
VEE
C
IDD
VEE
C
VOS
3.0
Static, No Load
Static, No Load
Logic Inputs
Logic Inputs
Logic Inputs
Logic Inputs
0
2
0
0.7 VDD
VEE
0.8 VDD
10
10
450
3.2
-22
-20
VIN = 0V to 5V
VIN = 0V to 5V
IL = 10µA
IL = 10µA @ 25°C
VOH = 4.5
VOL = 0.4
See Fig. 2
See Fig. 2
See Fig. 2
See Fig. 4
7.0
200
120
0.8
VDD
0.3 VDD
VDD
0.6 VDD
VDD
100
10
15
600
-3.0
-21
1.8
25
-21.5
V
µA
µA
V
V
V
V
V
V
nA
µA
pF
K
W
W
mA
mA
V
mA
V
mV
HOLT INTEGRATED CIRCUITS
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