The HI-8020 & HI-8120 high voltage display drivers
are functional replacements for the AMI S5420 and
Micrel MIC8013/8014 series. These CMOS prod-
ucts are designed to drive liquid crystal displays by
converting 5 volt serial data to parallel segment and
backplane waveforms with amplitudes up to 30 volts.
The HI-8020 & HI-8120 differ from the HI-8010 by
only the shift register clock and chip select gating
logic. The HI-8020 has TTL logic inputs whereas the
HI-8120 has CMOS logic inputs.
Both devices can drive up to 38 segments and have 3
possible shift register data taps to provide options to
cascade devices for larger displays. Data is clocked
into a 38 stage shift register and parallel latched
before the output translators by a Load input.
The HI-8020 & HI-8120 are available in ceramic
leadless chip carriers and plastic PLCC packages.
S27
S28
S29
S30
S31
S32
N/C
V
SS
CS
CL
LD
7
8
9
10
11
12
13
14
15
16
17
HI-8020J-85
&
HI-8120J-85
44 - PIN
PLASTIC
PLCC
18 19 20 21 22 23 24 25 26 27 28
37
36
35
34
33
32
31
30
29
S17
S16
S15
V
EE
S14
S13
S12
S11
S10
S9
S8
FEATURES
!
5 volt input translated to 30 volts or less
!
Pin-out adaptable to drive 30, 32 or 38
LCD segments
!
RC oscillator or high voltage (BP) clock input
!
TTL compatible inputs (HI-8020 only)
!
CMOS compatible inputs (HI-8120 only)
!
Low power consumption
!
Industrial (-40°C to +85°C) & Military (-55°C
to +125°C) temperature ranges
!
Pin for pin compatible with the Micrel
MIC8010/8011 series and the AMI S4520
series drivers
!
Cascadable
!
Military level processing available
(See page 4 for additional package pin configurations)
FUNCTIONAL BLOCK DIAGRAM
DIN
Þ
CL
Þ
CS
Þ
LE
DATA IN
DIN
LCDØ
LCDØOPT
V
DD
S1
S2
S3
S4
S5
S6
S7
38 Stage
Shift Register
CLK
Þ
DOUT 38
Þ
DOUT 32
Þ
DOUT 30
LD
Þ
LCDØ OPT
Þ
LCDØ
Þ
Oscillator
Divider
Vo l t a g e
Tr a n s l a t o r
38 Bit Latch
Vo l t a g e
Tr a n s l a t o r s
H i g h Vo l t a g e
Drivers
APPLICATIONS
!
!
!
!
Dichroic Liquid Crystal Displays
Standard Liquid Crystal Displays
Vacuum Fluorescent Displays
MEMS Drivers
H i g h Vo l t a g e
B u ff e r
Þ
BP
SEGMENTS
(DS8020 Rev. E)
HOLT INTEGRATED CIRCUITS
www.holtic.com
09/06
HI-8020/HI-8120 Series
FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (CS)
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (CL) input. A Logic "1" present at the Load (LD) input
will cause a parallel transfer of data from the shift register to
the data latch. If the Load (LD) input is held high while data
is clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8020 and
CMOS compatible on the HI-8120.
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phase with the backplane.
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150K
W
resistor with a 470pF capacitor generates an
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30K
W
for proper self-oscillator
operation.
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc.(See Figures 2 & 3). Data out (DOUT) will change state
C
R
on the rising edge of the Clock (CL). Clock (CL), Load (LD)
and Chip Select (CS) should be tied in common with each
other, respectively, between all cascaded display drivers.
INTERNAL OSCILLATOR CIRCUIT
÷ 256
Q
LCDØ
LCDØ
OPT
TO BACKPLANE
TRANSLATOR
AND DRIVER
Figure 1.
TIMING DIAGRAM
CL
INPUT
t
CL
DIN
INPUT
VALID
VALID
t
DS
t
DH
CS
INPUT
t
CSS
t
CSH
LD
INPUT
t
LCS
t
CSL
t
CDO
DOUT
OUTPUT
VALID
VALID
t
LS
t
LW
VALID
HOLT INTEGRATED CIRCUITS
2
HI-8020/HI-8120 Series
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V
Supply Voltage
VDD........................ 0V to 7V
VEE................VDD-35V to 0V
Voltage at any input, except LCDØ..-0.3 to VDD+0.3V
Voltage at LCDØ input...............VDD-35 to VDD+0.3V
DC Current any input pin...................................10 mA
Power Dissipation......................................................300 mW
Operating Temperature Range - Industrial........-40° to +85°C
Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C
Storage Temperature Range...........................-65° to +150°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
Supply Current
SYMBOL
VDD
IDD
IEE
CONDITION
Static, No Load
Static, No Load f
BP
=100Hz
MIN
3.0
TYP
MAX
7.0
225
150
UNITS
V
µA
µA
V
V
V
V
V
V
µA
pF
K
W
W
mA
mA
Input Low Voltage, HI-8020 (except LCDØ)
Input High Voltage, HI-8020 (except LCDØ)
Input Low Voltage, HI-8120 (except LCDØ)
Input High Voltage, HI-8120 (except LCDØ)
Input Low Voltage (LCDØ)
Input High Voltage (LCDØ)
Input Current
Input Capacitance (not tested)
Segment Output Impedance
Backplane Output Impedance
Data Out Current:
VIL
TTL
VIH
TTL
VIL
CMOS
VIH
CMOS
VILX
VIHX
IIN
CI
RSEG
RBP
IDOH
IDOL
IL = 10µA
IL = 10µA
Source Current, VOH = 4.5V
Sink Current, VOL = 0.5V
VIN = 0 to 5V
0
2
0
0.7 VDD
VEE
3.5
0.8
VDD
0.3 VDD
VDD
3
VDD
1
5
10
450
15
600
-0.6
0.6
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Clock Period
Clock Pulse Width
Data In - Setup
Data In - Hold
Chip Select - Setup to Clock
Chip Select - Hold to Clock
Load - Setup to Clock
Chip Select - Setup to Load
Load Pulse Width
Chip Select - Hold to Load
SYMBOL
t
CL
t
CW
t
DS
t
DH
t
CSS
t
CSH
t
LS
t
CSL
t
LW
t
LCS
VDD
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
MIN
1200
520
50
400
200
450
500
300
500
300
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Out Valid, from Clock
t
CDO
5V
800
ns
HOLT INTEGRATED CIRCUITS
3
HI-8020/HI-8120 Series
CASCADING - EXT. OSCILLATOR
LD
CL
CS
CS
DIN
CL
LD
DOUT
CS
DIN
CL
LD
DOUT
CS
DIN
CL
LD
DOUT
CASCADING - RC OSCILLATOR
LD
CL
CS
CS
DIN
150KW
CL
LD
DOUT
CS
DIN
CL
LD
DOUT
CS
DIN
CL
LD
DOUT
HI-8020J-85
LCDØ
BP
HI-8020J-85
LCDØ
BP
HI-8020J-85
LCDØ
BP
HI-8120J-85
LCDØ
LCDØ OPT
BP
HI-8120J-85
LCDØ
LCDØ OPT
BP
HI-8120J-85
LCDØ
LCDØ OPT
BP
470pf
SEGMENTS
1 - 33
SEGMENTS BACK
33 - 64
PLANE
SEGMENTS
65 - 96
SEGMENTS
1 - 32
SEGMENTS BACK
33 - 64
PLANE
SEGMENTS
65 - 96
Figure 2
Figure 3
PIN DESCRIPTIONS
SYMBOL
VSS
CS
CL
LD
DIN
LCD0
LCD0OPT
VDD
VEE
DOUT
BP
Segments
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
OUTPUT
0 Volts
Logic input
Logic input
Logic input
Logic input
Analog input
Analog output
5 Volts
0 Volts to -30 Volts
Logic output
Display drive output
Display drive output
DESCRIPTION
Chip select
Clocks shift register on negative edge and DOUT pins on positive edge
Segment outputs equal shift register data if Load is high
Shift register data input
Display clock input and is always bonded out. Can swing from VEE to VDD
Bonded out only if an RC oscillator is required
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38
Low resistance drive for the backplane and swings from VDD to VEE
High resistance drive for each segment and swings from VDD to VEE
ADDITIONAL HI-8020/HI-8120 PIN CONFIGURATIONS
(See page 1 for the 44-Pin Plastic PLCC)
S26
S25
S24
S23
S22
S21
S20
DOUT 38
BP
S19
S18
S17
S26
S25
S24
S23
S22
S21
S20
DOUT 38
BP
S19
S18
S17
S16
S15
V
EE
S14
S13
S12
S11
S10
S9
S8
S7
S6
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
V
SS
CS
7
8
9
10
11
12
13
14
15
16
17
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
V
SS
CS
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
6
5
4
3
2
1 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
HI-8020S-61
HI-8120S-61
HI-8020SM-62
&
HI-8120SM-62
48 - PIN
CERAMIC
LCC
HI-8020S-63
HI-8120S-63
HI-8020SM-64
&
HI-8120SM-64
48 - PIN
CERAMIC
LCC
18
31
19 20 21 22 23 24 25 26 27 28 29 30
18
31
19 20 21 22 23 24 25 26 27 28 29 30
S16
S15
V
EE
S14
S13
S12
S11
S10
S9
S8
S7
S6
CL
LD
DIN
LCDØ /
LCDØOPT
HOLT INTEGRATED CIRCUITS
4
CL
LD
DIN
LCDØ
V
DD
S37
S38
S1
S2
S3
S4
S5
V
DD
S37
S38
S1
S2
S3
S4
S5
HI-8020/HI-8120 Series
ORDERING INFORMATION
HI - 8XXX J X - 85 (44-pin Plastic J Lead)
PART
NUMBER
LEAD
FINISH
Blank
F
PART
NUMBER
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
INPUT
LOGIC
NUMBER OF
SEGMENTS
MASTER/
SLAVE
TEMPERATURE
RANGE
FLOW
BURN
IN
8020
8120
TTL
CMOS
32
32
BOTH
BOTH
-40°C TO +85°C
-40°C TO +85°C
I
I
NO
NO
HI - 8XXX XX - XX (48-pin Ceramic Leadless Chip Carrier)
嵌入式系统
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