HI-8482
August 2006
ARINC 429 DUAL LINE RECEIVER
GENERAL DESCRIPTION
The HI-8482 bus interface unit is a silicon gate CMOS de-
vice designed as a dual differential line receiver in accor-
dance with the requirements of the ARINC 429 bus speci-
fication. The device translates incoming ARINC 429 sig-
nals to normal CMOS/TTL levels on each of its two inde-
pendent receive channels. The HI-8482 is also function-
ally equivalent to the Fairchild/Raytheon RM3183.
The self-test inputs force the outputs to either a ZERO,
ONE, or NULL state for system tests. While in self-test
mode, the ARINC inputs are ignored.
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with exter-
nal capacitors.
The HI-8482 line receiver is one of several options of-
fered by Holt Integrated Circuits to interface to the ARINC
bus. The digital data processing for serial-to-parallel con-
version and clock recovery can be accomplished with the
HI-6010, HI-8683 or similar devices.
The HI-8482 is available in a variety of ceramic & plastic
packages including Small Outline (SOIC), J-Lead PLCC,
Cerquad, DIP & Leadless Chip Carrier (LCC).
PIN CONFIGURATIONS
(Top Views)
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
HI-8482J
HI-8482JT
20 - PIN
PLASTIC
J-LEAD PLCC
+V
L
- 9
N/C - 10
OUT1B - 12
+V
S
- 11
20 - TESTB
3 - CAP2B
2 - TESTA
1 - -V
S
N/C - 13
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +V
S
FEATURES
!
Converts ARINC 429 levels to digital data
!
Direct replacement for the RM3183
!
Greater than 2 volt receiving hysteresis
!
TTL and CMOS outputs and test inputs
!
Military screening available
!
20-Pin SOIC, PLCC, CERQUAD, DIP &
LCC packages are available
-V
S
- 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+V
L
- 9
N/C - 10
HI-8482PSI
HI-8482PST
20 - PIN
PLASTIC
SMALL
OUTLINE
(SOIC) - WB
(See page 6 for additional Package Pin Configurations)
TRUTH TABLE
ARINC INPUTS
V (A) - V (B)
Null
Zero
One
Don't Care
Don't Care
Don't Care
TEST INPUTS
TEST A
0
0
0
0
1
1
OUTPUTS
OUT A
0
0
1
0
1
0
TEST B
0
0
0
1
0
1
OUT B
0
1
0
1
0
0
(DS8482 Rev. F)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/06
HI-8482
FUNCTIONAL DESCRIPTION
The HI-8482 contains two independent ARINC 429 receive
channels. The diagram in Figure 1 illustrates a typical HI-
8482 receive channel.
The differential ARINC signal input is converted to a positive
signal referenced to ground through level shifters and a
unity gain differential amplifier.
A positive differential input signal is converted to a positive
signal on the plus output of the differential amplifier. This
output is proportional in amplitude to the original input
signal. At the same time, the corresponding MINUS output
is pulled to GND. Likewise when a negative input signal is
present at the ARINC inputs, a positive signal is present on
the MINUS output and the PLUS output is pulled to GND.
The outputs of the differential amplifier are compared with
the ONE, ZERO and NULL threshold levels to produce the
appropriate logic level on the OUTA and OUTB outputs of
the device. The ARINC clock signal may be recovered
through a NOR function of OUTA and OUTB.
The test inputs logically disconnect the outputs of the
comparators from OUTA and OUTB and force the device
outputs to one of the three valid states (Figure 5). This
alleviates having to ground the ARINC inputs during test
mode operation.
ARINC LEVELS
The ARINC 429 specification requires the following
detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5V to +13V
+2.5V to -2.5V
-6.5V to -13V
The HI-8482 guarantees recognition of these levels with a
common mode voltage with respect to GND less than
±5V for the worst case condition.
NOISE
The input hysteresis is set to reject voltage level transi-
tions in the undefined region between the maximum
ZERO level and the minimum NULL level and the unde-
fined region between the maximum NULL level and the
minimum ONE level. Therefore, once a valid input
differential voltage threshold is detected, the outputs will
remain at a valid logic state until a new valid input voltage
is detected.
In addition to the hysteresis, the CAPA and CAPB pins
make it possible to add simple RC filters to the ARINC
inputs.
+V
L
+Vs
TYPICAL CHANNEL
TESTA
TESTB
INA
CAPA
PLUS
LEVEL
SHIFT
Detect
Level
Comp
DIFF
AMP
OUTA
INB
CAPB
LEVEL
SHIFT
MINUS
Comparators
w / hysteresis
Comp
OUTB
Detect
Level
-Vs
FIGURE 1 - BLOCK DIAGRAM
GND
HOLT INTEGRATED CIRCUITS
2
HI-8482
ground (GND) connection should be sturdy and isolated from large
switching currents to provide a quiet ground reference.
The HI-8482 can be used with HI-3182 or HI-8585 Line Drivers to
provide a complete analog ARINC 429 interface solution. A simple
application, which can be used in systems requiring a repeater
type circuit for long transmissions or for test interfaces, is given in
Figure 3. More HI-3182 or HI-8585 drivers may be added to test
multiple ARINC channels, as shown.
TYPICAL APPLICATIONS
APPLICATIONS
The standard connections for the HI-8482 are shown in Figure 2.
Decoupling of the supply should be done near the IC to avoid
propagation of noise spikes due to switching transients. The
+5V
+15V
HI-8482
ARINC
CHANNEL 1
39 pF
IN1A
IN1B
CAP1A
39 pF
OUT1A
OUT1B
A
B
CHANNEL 1
DATA OUT
TO LOGIC
CAP1B
IN2A
IN2B
OUT2A
OUT2B
A
B
CHANNEL 2
DATA OUT
TO LOGIC
ARINC
CHANNEL 2
39 pF
39 pF
CAP2A
CAP2B
TESTA
N/C
TESTB
N/C
LOGIC
TEST
INPUTS
-15V
FIGURE 2 - ARINC RECEIVER STANDARD CONNECTIONS
ARINC
INPUT
CHANNEL
IN1A
IN1B
OUT1A
OUT1B
DATA (A)
DATA (B)
AOUT
BOUT
A
B
ARINC
OUTPUT
CHANNEL 1
1/2
HI-8482
DATA (A)
DATA (B)
HI-3182
or HI-8585
AOUT
BOUT
A
B
ARINC
OUTPUT
CHANNEL 2
HI-3182
or HI-8585
TO ADDITIONAL
CHANNELS
FIGURE 3 - ARINC REPEATER CIRCUIT
HOLT INTEGRATED CIRCUITS
3
HI-8482
PIN DESCRIPTION TABLE
SYMBOL FUNCTION
CAP1A
CAP1B
CAP2A
CAP2B
GND
IN1A
IN1B
IN2A
INPUT
INPUT
INPUT
INPUT
POWER
INPUT
INPUT
INPUT
DESCRIPTION
Filter capacitor input for terminal A of
channel 1
Filter capacitor input for terminal B of
channel 1
Filter capacitor input for terminal A of
channel 2
Filter capacitor input for terminal B of
channel 2
0 Volts
ARINC input terminal A of channel 1
ARINC input terminal B of channel 1
ARINC input terminal A of channel 2
SYMBOL FUNCTION
IN2B
OUT1A
OUT1B
OUT2A
OUT2B
TESTA
TESTB
+V
L
+Vs
-Vs
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
POWER
POWER
POWER
DESCRIPTION
ARINC input terminal B of channel 2
TTL output terminal A of channel 1
TTL output terminal B of channel 1
TTL output terminal A of channel 2
TTL output terminal B of channel 2
Test input terminal A
Test input terminal B
+5 Volts ±10%
+12 Volts ±10% or +15 Volts ±10%
-12 Volts ±10% or -15 Volts ±10%
TIMING DIAGRAMS
+10V
ARINC
DIFFERENTIAL
INPUT
0V
-10V
t
PLH
50%
t
r
90%
10%
t
f
OUTA
t
PHL
t
PLH
t
PHL
50%
OUTB
FIGURE 4
+5V
TESTA
0V
+5V
TESTB
0V
t
TLH
50%
t
r
90%
10%
t
f
OUTA (test)
t
THL
t
TLH
t
THL
50%
OUTB (test)
FIGURE 5
HOLT INTEGRATED CIRCUITS
4
HI-8482
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to Gnd = 0V)
Supply Voltage, +V
S
:......................................................................+20 VDC
-V
S
: .......................................................................-20 VDC
+V
L
:........................................................................+7 VDC
Operating Temperature Range: (Industrial) .........................-40°C to +85°C
(Hi-Temp) ........................-55°C to +125°C
(Military) ..........................-55°C to +125°C
Internal Power Dissipation: ..............................................................900mW
Voltage at ARINC Inputs: .......................................................-29V to +29V
Voltage at Any Other Input:.............................................-0.3V to V
L
+ 0.3V
Output Short Circuit Protected: .............................................Not Protected
Storage Temperature Range: .........................................-65°C to +150°C
Soldering Temperature: (Ceramic).................................30 sec. at +300°C
(Plastic - leads)........................10 sec. at +280°C
(Plastic - body) ................................+220°C Max.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
±12 < V
S
< ±15, V
L
= +5V, Operating temperature range (unless otherwise noted)
PARAMETERS
ARINC inputs - IN1A, IN1B, IN2A, IN2B
V(A) - V(B)
V(A) - V(B)
V(A) - V(B)
(|V(A)| - |V(B)|) / 2
Input resistance - input A to input B
Input resistance - input A or B to Gnd
Input capacitance - input A to B
Input capacitance - input A or B to Gnd
Test inputs - TESTA, TESTB
Logic 1 input voltage
Logic 0 input voltage
Logic 1 input current (magnitude)
Logic 0 input current
Outputs - OUT1A, OUT1B, OUT2A, OUT2B
Voltage - sourcing 100µA
Voltage - sourcing 2.8mA
Voltage - sinking 100µA
Voltage - sinking 2.0mA
Rise time
Fall time
Propagation delay - low to high (ARINC)
Propagation delay - high to low (ARINC)
Propagation delay - low to high (TESTA/B)
Propagation delay - low to high (TESTA/B)
Supply current
+VS current
+VS current
-VS current
-VS current
+VL current
+VL current
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIH
VIL
VNULL
VCM
RI
RG
CI
CG
OUTA = 1
OUTB = 1
OUTA = OUTB = 0
Frequency = 80KHz
Supply pins floating
Supply pins floating
Filter caps disconnected
Filter caps disconnected
6.5
-6.5
-2.5
30K
19K
-
-
see note 1
see note 1
10
-10
0
±5
50K
25K
5
5
13
-13
2.5
10
10
volts
volts
volts
volts
ohms
ohms
pF
pF
VIH
VIL
IIH
IIL
ARINC inputs to Gnd, TA = 25°C
ARINC inputs to Gnd, TA = 25°C
VIH = 2.7V
VIL = 0V
2.7
5
0.5
0.8
15
1
volts
volts
µA
µA
VOH
VOH
VOL
VOL
tr
tf
tPLH
tPHL
tTLH
tTHL
TA = 25°C
Full temperature range
TA = 25°C
Full temperature range
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C and filter caps disconnected
CL = 50pF, TA = 25°C and filter caps disconnected
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C
4
3.5
0.08
0.8
70
70
40
30
600
600
50
50
volts
volts
volts
volts
ns
ns
ns
ns
ns
ns
IDD
IDD
IEE
IEE
ICC
ICC
±VS
±VS
±VS
±VS
±VS
±VS
=
=
=
=
=
=
±15V,
±12V,
±15V,
±12V,
±15V,
±12V,
TA
TA
TA
TA
TA
TA
=25°C,
=25°C,
=25°C,
=25°C,
=25°C,
=25°C,
TESTA
TESTA
TESTA
TESTA
TESTA
TESTA
and TESTB
and TESTB
and TESTB
and TESTB
and TESTB
and TESTB
=
=
=
=
=
=
0V
0V
0V
0V
0V
0V
3.7
3
8.7
7.4
9
8.6
7
6
15
14
20
18
mA
mA
mA
mA
mA
mA
Notes:
1. Guaranteed by design.
HOLT INTEGRATED CIRCUITS
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
