HI-8588-10
July 2006
ARINC 429 LINE RECEIVER
PIN CONFIGURATION
VCC - 1
TESTA - 2
RINB - 3
RINA - 4
8 - TESTB
7 - ROUTB
6 - ROUTA
5 - GND
DESCRIPTION
The HI-8588-10 ARINC 429 bus interface receiver is simi-
lar to the HI-8588 with the exception that it allows an exter-
nal 10 Kohm resistor in series with each ARINC input with-
out affecting the ARINC input thresholds. The product is
especially useful in applications where lightning protection
circuitry is also required. In addition, the test inputs force
both of the outputs to zero instead of open circuit. The ana-
log/digital CMOS product requires only a 5 volt supply and
is available in a 8-pin SOIC package.
Each side of the ARINC bus must be connected through a
10 Kohm series resistor in order for the chip to detect the
correct ARINC levels. The typical 10 volt differential signal
is translated and input to a window comparator and latch.
The comparator levels are set so that with the external
10 Kohm resistors they are just below the standard 6.5 volt
minimum ARINC data threshold and just above the stan-
dard 2.5 volt maximum ARINC null threshold.
The TESTA and TESTB inputs bypass the analog inputs for
testing purposes. Also if TESTA and TESTB are both taken
high, the digital outputs are forced to zero.
See Holt Application Note AN-300 for more information on
lightning protection.
HI-8588PSI-10, HI-8588PST-10 & HI-8588PSM-10
8 - PIN PLASTIC NARROW BODY SOIC
SUPPLY VOLTAGES
vcc
= 5.0V ± 5%
FUNCTION TABLE
RECEIVER
RINA
-1.25V to 1.25V
-3.25V to -6.5V
3.25V to 6.5V
X
X
X
RINB
-1.25V to 1.25V
3.25V to 6.5V
-3.25V to -6.5V
X
X
X
TESTA
0
0
0
0
1
1
TESTB
0
0
0
1
0
1
ROUTA ROUTB
0
0
1
0
1
0
0
1
0
1
0
0
FEATURES
!
!
!
!
!
!
ARINC 429 line receiver interface in a
small outline package
Lightning protection simplified with the
ability to add 10 Kohm external series
resistors
Receiver input hystersis at least 2 volts
PIN
PIN DESCRIPTION TABLE
SYMBOL
VCC
TESTA
RINB
RINA
GND
ROUTA
ROUTB
TESTB
FUNCTION
SUPPLY
LOGIC INPUT
ARINC INPUT
ARINC INPUT
POWER
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC INPUT
CMOS
RECEIVER B INPUT
RECEIVER A INPUT
GROUND
RECEIVER CMOS OUTPUT A
RECEIVER CMOS OUTPUT B
CMOS
DESCRIPTION
5 VOLT SUPPLY
1
2
3
4
5
6
7
8
Test inputs bypass analog inputs and
force digital outputs to an one, zero or
null state
Plastic and ceramic package options -
surface mount and DIP
Mil processing available
(DS8588-10, Rev. C)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/06
HI-8588-10
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 35K
W
of resis-
tance of which 25K
W
is internal to the chip. The series re-
sistance is connected to level translators whose resistance
to Ground is typically 10K
W
. In order for the voltage trans-
lation not to be adversely affected, an external 10K
W
series
resister must be added to each ARINC input. The
HI-8588-10 device is typically chosen for applications
where external series resistors are required in its lightning
protection circuitry.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
between VCC and Ground. The nominal settings corre-
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. Unlike the HI-8588, if TESTA and TESTB
are both One, the HI-8588-10 outputs are pulled low in-
stead of being tri-stated. This allows the digital outputs
of a transmitter to be connected to the test inputs through
control logic for self-test purposes.
ONE
S
R
Q
LATCH
TEST
ROUTA
TESTA
TESTB
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
NULL
TEST
ZERO
S
R
Q
LATCH
ROUTB
TESTA
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
HARDWIRE
OR
DRIVE FROM LOGIC
{
10KW
10KW
2
8
4
3
VCC
TESTA
TESTB
ROUTA
ROUTB
6
7
RXD1
RXD0
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8588-10 interfacing an ARINC receive
channel to the HI-6010 which in turn inter-
faces to an 8-bit bus.
HI-8588-10
RINA
RINB GND
ARINC
Channel
HI-6010
5
15V
1
6
ARINC
Channel
SLP1.5
TXAOUT
V+
TX1IN
TX0IN
V-
8 BIT BUS
8
3
2
TXD1
TXD0
7
HI-8586
TXBOUT
GND
4
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8588-10
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground
Supply voltages
VCC...................................................7V
ARINC input - pins 3 & 4
Voltage at either pin......+29V to -29V
DC current per input pin................ ±10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
NOTE: Stresses above absolute maximum
ratings or outside recommended operating con-
ditions may cause permanent damage to the
device. These are stress ratings only. Opera-
tion at the limits is not recommended.
Supply Voltages
VCC........................................5V ± 5%
Temperature Range
Industrial Screening........-40°C to +85°C
Hi-Temp Screening.......-55°C to +125°C
Military Screening.........-55°C to +125°C
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
ARINC input voltage
one or zero
null
common mode
logic input voltage
high
low
ARINC input resistance
RINA to RINB
RINA or RINB to Gnd or VCC
logic input current
source
sink
logic output drive current
one
zero
Current drain
operating
SYMBOL
TEST CONDITIONS
diff. volt. thru 10K
W
, pins 3 & 4
"
"
"
with respect to Ground
MIN
TYP
MAX
UNITS
V DIN
V NIN
VCOM
V IH
V IL
R DIFF
R SUP
I IH
I IL
I OH
I OL
I CC1
6.5
-
-
10
-
-
13
2.5
5.0
volts
volts
volts
3.5
-
-
-
-
1.5
volts
volts
supplies floating & series 10KW
"
V IN = 0 V
V IN = 5 V
V = 4.6V
OH
VOL = 0.4V
pins 2, 8 = 0V; pins 3, 4 open
"
"
30
19
75
40
-
-
Kohm
Kohm
mA
mA
-
-
-
-
0.1
0.1
-
3.6
-1.6
5.6
-0.8
-
mA
mA
-
2.3
6.3
mA
HOLT INTEGRATED CIRCUITS
3
HI-8588-10
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
Receiver propagation delay
Output high to low
Output low to high
Receiver output transition times
Output high to low
Output low to high
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
Notes: 1. Guaranteed but not tested
SYMBOL TEST CONDITIONS
defined in Figure 3, C L= 50pF
t phlr
t plhr
t fr
t rr
CAD
CAS
C IN
MIN
TYP
MAX
UNITS
-
-
600
600
-
-
ns
ns
-
-
-
-
-
50
50
5
-
-
80
80
10
10
10
ns
ns
pF
pF
pF
VDIFF
pin 4 - pin 3
t
plhr
t
phlr
90%
10V
0V
-10V
t
rr
pin 6
t
plhr
10%
5V
0V
t
fr
t
phlr
pin 7
FIGURE 3 - RECEIVER TIMING
5V
0V
ORDERING INFORMATION
HI - 8588 xx x x - 10
PART
NUMBER
LEAD
FINISH
Blank
F
PART
NUMBER
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
T
M
PART
NUMBER
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
PACKAGE
DESCRIPTION
I
T
M
NO
NO
YES
PD
PS
CR
8 PIN PLASTIC DIP (not available with “M” flow)
8 PIN PLASTIC NARROW BODY SOIC
8 PIN CERDIP (not available Pb-free)
HOLT INTEGRATED CIRCUITS
4
HI-8588-10 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC DIP
Package Type: 8P
.385
±.015
(4.699
±.381)
.250 ± .010
(6.350
±.254)
.100
±.010
(3.540
±.254)
.300
±.010
(7.620
±.254)
.025
±.010
(.635 ± .254)
.0115
±.0035
(.292
±.089)
.055
±.010
(1.397
±.254)
.335
±.035
(8.509
±.889)
7° TYP.
.135
±.015
(3.429
±.381)
.1375
±.0125
(3.493
±.318)
.019
±.002
(.483
±.102)
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
.1935 ± .0035
(4.915 ± .085)
Package Type: 8HN
.0086 ± .0012
(.2184 ± .0305)
.236 ± .008
(5.994 ± .203)
P
IN
1
.1535 ± .0035
(3.90 ± .09)
.0165 ± .0035
(.4191 ± .0889)
Detail A
.055 ± .005
(1.397 ± .127)
0° to 8°
.050 ± .010
(1.27 ± .254)
.033 ± .017
(.8382 ± .4318)
.0069 ± .0029
(.1753 ± .0737)
Detail A
HOLT INTEGRATED CIRCUITS
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
