HI-8581, HI-8589
September 2006
ARINC 429 LINE DRIVER AND DUAL RECEIVER
FEATURES
!
ARINC specification 429 compliant
!
Direct receiver and transmitter interface to
ARINC bus in a single device
!
16-Bit parallel data bus
!
Timing control 10 times the data rate
!
Selectable data clocks
!
Receiver error rejection per ARINC
specification 429
!
Automatic transmitter data timing
!
Self test mode
!
Parity functions
!
Low power
!
Industrial & full military temperature ranges
GENERAL DESCRIPTION
The HI-8581 and HI-8589 from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. Both
devices provide two receivers, an independent transmitter
and line driver capability in a single package. The receiver
input circuitry and logic are designed to meet the
ARINC 429 specifications for loading, level detection,
timing, and protocol. The transmitter section provides the
ARINC 429 communication protocol and the line driver
circuits provide the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces
with CMOS and TTL.
The HI-8581 has 37.5 ohms in series with each line driver
output. The HI-8589 provides the option to bypass most of
the internal output resistance so that external series
resistance may be added for lighting protection and still
match the 75 ohm characteristic impedance of the ARINC
bus.
Each independent receiver monitors the data stream with
a sampling rate 10 times the data rate. The sampling rate
is software selectable at either 1MHz or 125KHz. The
results of a parity check are available as the 32nd ARINC
bit. The HI-8581 and HI-8589 examine the null and data
timings and will reject erroneous patterns. For example,
with a 125 KHz clock selection, the data frequency must
be between 10.4 KHz and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of
the transmitter is software selectable by dividing the
master clock, CLK, by either 10 or 80. The master clock is
used to set the timing of the ARINC transmission within the
required resolution.
PIN CONFIGURATION
(Top View)
- 429DI2(A)
- 429DI1(B)
- 429DI1(A)
- VCC
- N/C
- MR
- TXCLK
- CLK
- N/C
- N/C
- CWSTR
429DI2(B) - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
44
43
42
41
40
39
38
37
36
35
34
HI-8581PQI
HI-8589PQI
&
HI-8581PQT
HI-8589PQT
33 - ENTX
32 - N/C
31 - V+
30 - TXB(OUT)
29 - TXA(OUT)
28 - V-
27 - GND
26 - TX/R
25 - PL2
24 - PL1
23 - BD00
APPLICATIONS
!
Avionics data communication
!
Serial to parallel conversion
!
Parallel to serial conversion
HOLT INTEGRATED CIRCUITS
www.holtic.com
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 12 for additional pin configurations)
(DS8581 Rev. G)
BD10 - 12
BD09 - 13
BD08 - 14
BD07 - 15
BD06 - 16
GND - 17
BD05 - 18
BD04 - 19
BD03 - 20
BD02 - 21
BD01 - 22
09/06
HI-8581, HI-8589
PIN DESCRIPTION
SIGNAL
V
CC
V+
V-
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
TX/R
PL1
PL2
TXA(OUT)
TXB(OUT)
ENTX
CWSTR
CLK
TX CLK
MR
FUNCTION
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
+5V ±5%
+9.5V to +10.5V
-9.5V to -10.5V
DESCRIPTION
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Line driver output - A side
Line driver output - B side
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
Both the HI-8581and HI-8589 contain 10 data flip flops whose
D inputs are connected to the data bus and clocks connected to
CWSTR. Each flip flop provides options to the user as follows:
DATA
BUS
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
DATA
BUS
PIN
BDO5
FUNCTION CONTROL
DESCRIPTION
If enabled, the transmitter’s digital
outputs are internally connected
to the receiver logic inputs
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
If enabled, ARINC bits 9 and
10 must match the next two
Control word bits
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
CLK is divided either by 10 or
80 to obtain XMTR data clock
CLK is divided either by 10 or
80 to obtain RCVR data clock
ARINC
BIT
SELF TEST
0 = ENABLE
BYTE 2
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO6
RECEIVER 1
DECODER
1 = ENABLE
BDO7
-
-
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
BDO8
-
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
BD10
-
-
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
BD11
-
-
BD12
INVERT
XMTR
PARITY
XMTR DATA
CLK SELECT
RCVR DTA
CLK SELECT
1 = ENABLE
The HI-8581 and HI-8589 guarantee recognition of these levels with
a common mode Voltage with respect to GND less than ±4V for the
worst case condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BD13
0 = ÷10
1 = ÷80
0 = ÷10
1 = ÷80
BD14
v
cc
429DI1 (A)
OR
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
429DI2 (A)
GND
NULL
v
cc
429DI1 (B)
OR
ZEROES
429DI2 (B)
GND
FIGURE 1.
ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
HIGH SPEED
LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
BIT RATE
10 ± 5 µsec
PULSE RISE TIME
1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE FALL TIME
1.5 ± 0.5 µsec
5 µsec ± 5%
34.5 to 41.7 µsec
PULSE WIDTH
The HI-8581 and HI-8589 accept signals that meet these specifica-
tions and rejects outside the tolerances. The way the logic opera-
tion achieves this is described below:
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word
gap, three consecutive Nulls must be found in both the upper
and lower bits of the sampling shift register. In this manner the
minimum pulse width is guaranteed.
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
HIGH SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the par-
ity bit, ARINC bit 32. If the result is odd, then "0" will appear in the
32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates
an End of Sequence (EOS). If the receiver decoder is enabled
and the 9th and 10th ARINC bits match the control word pro-
gram bits or if the receiver decoder is disabled, then EOS clocks
the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go
low. The data flag for a receiver will remain low until after both
ARINC bytes from that receiver are retrieved. This is accom-
plished by first activating EN with SEL, the byte selector, low to
retrieve the first byte and then activating EN with SEL high to re-
trieve the second byte. EN1 retrieves data from receiver 1 and
EN2 retrieves data from receiver 2.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
TO PINS
SEL
EN
D/R
DECODER
CONTROL
BITS
MUX
CONTROL
32 TO 16 DRIVER
CONTROL
BIT BD14
CLOCK
OPTION
CLOCK
CLK
/
LATCH
ENABLE
CONTROL
BITS 9 & 10
32 BIT LATCH
BIT
COUNTER
AND
END OF
SEQUENCE
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT CLOCK
EOS
EOS
ONES
WORD GAP
WORD GAP
TIMER
BIT CLOCK
SHIFT REGISTER
START
END
NULL
SHIFT REGISTER
SEQUENCE
CONTROL
ZEROS
SHIFT REGISTER
ERROR
ERROR
DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
SELF TEST
If the BD05 control word bit is set low, the digital outputs of the
transmitter are internally connected to the logic inputs of the
receivers, bypassing the analog bus interface circuitry. Data to
Receiver 1 is as transmitted and data to Receiver 2 is the
complement. All data transmitted during self test is also present
on the TXA(OUT) and TXB(OUT) line driver outputs.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
BIT BD12
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either TXA(OUT) or TXB(OUT). The 31 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
31 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
TXA(OUT)
TXB(OUT)
WORD CLOCK
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
8 X 31 FIFO
ADDRESS
LOAD
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
TX/R
ENTX
FIFO
LOADING
SEQUENCER
PL1
PL2
DATA BUS
DATA
CLOCK
DATA CLOCK
DIVIDER
CLK
TX CLK
FIGURE 3.
TRANSMITTER BLOCK DIAGRAM
CONTROL BIT
BD13
HOLT INTEGRATED CIRCUITS
5
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