CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
DATA INPUTS
(Pins 13 to 24)
Input Voltage Bit ON Logic “1”
Input Voltage Bit OFF Logic “0”
Logic Current Bit ON Logic “1”
Logic Current Bit OFF Logic “0”
Resolution
OUTPUT
Unipolar Current
Bipolar Current
Resistance
Unipolar Offset (25
o
C)
T
A
= 25
o
C, V
CC
= +15V, V
EE
= -15V, Unless Otherwise Specified
HI-565AJ, HI-565AS
TEST CONDITIONS
MIN
TYP
MAX
MIN
HI-565AT
TYP
MAX
UNITS
(T
MlN
to T
MAX
)
(T
MlN
to T
MAX
)
(T
MlN
to T
MAX
)
(T
MlN
to T
MAX
)
(Note 2)
+2.0
-
-
-
12
-
-
0.01
-2.0
-
+5.5
+0.8
+1.0
-20
-
+2.0
-
-
-
12
-
-
0.01
-2.0
-
+5.5
+0.8
+1.0
-20
-
V
V
µA
µA
Bits
(All Bits ON)
(All Bits ON or OFF)
(Exclusive of Span
Resistors) (Note 2)
-1.6
±0.8
1.8K
-0.05
-0.07
-2.0
±1.0
2.5K
0.01
0.01
0.05
0.05
20
-
-2.4
±1.2
3.2K
0.05
0.07
0.15
0.25
-
+10
-1.6
±0.8
1.8K
-0.05
-0.07
-0.1
-0.2
-
-1.5
-2.0
±1.0
2.5K
0.01
0.01
0.05
0.05
20
-
-2.4
±1.2
3.2K
0.05
0.07
0.1
0.2
-
+10
mA
mA
Ω
% of FS
% of FS
% of FS
% of FS
pF
V
Bipolar Offset (25
o
C)
Bipolar Offset (T
MlN
to T
MAX
)
/883 Versions Only
Capacitance
Compliance Voltage
ACCURACY
(Error Relative to Full Scale)
Integral Non-Linearity
Integral Non-Linearity
/883 Versions Only
Differential Non-Linearity
Differential Non-Linearity
(25
o
C)
End Point Method
(T
MIN
to T
MAX
)
End Point Method
25
o
C
T
MIN
to T
MAX
(T
MIN
to T
MAX
)(Note 2)
(Figure 2, R
3
= 50Ω)
-0.15
-0.25
-
-1.5
-
-
-
±0.25
(0.006)
±0.50
(0.012)
±0.50
±0.50
(0.012)
±0.75
(0.018)
±0.75
-
-
-
±0.12
(0.003)
±0.25
(0.006)
±0.25
±0.25
(0.006)
±0.50
(0.012)
±0.50
LSB
% of FS
LSB
% of FS
LSB
MONOTONICITY GUARANTEED
2
HI-565A
Electrical Specifications
PARAMETER
TEMPERATURE COEFFIClENTS
Unipolar Offset Drift
Bipolar Zero Drift
Gain Drift, Uni- and Bipolar (Full Scale)
Differential Nonlinearity Error Drift
SETTLING TIME
T0
±0.5
LSB
With High, Z External Load
With 75Ω External Load
(Notes 2, 3)
(Notes 2, 3)
-
-
350
150
500
250
-
-
350
150
500
250
ns
ns
Internal Reference
Internal Reference
Int. Ref.
-
-
-
-
1
5
15
2
2
10
40
-
-
-
-
-
1
5
10
2
2
10
25
-
ppm/
o
C
ppm/
o
C
ppm/
o
C
ppm/
o
C
T
A
= 25
o
C, V
CC
= +15V, V
EE
= -15V, Unless Otherwise Specified
(Continued)
HI-565AJ, HI-565AS
TEST CONDITIONS
MIN
TYP
MAX
MIN
HI-565AT
TYP
MAX
UNITS
FULL SCALE TRANSITION
From 50% of Logic Input to 90% of Analog Output
Rise Time
Fall Time
POWER REQUIREMENTS
I
CC
I
EE
POWER SUPPLY GAIN SENSITIVITY
(Note 4)
V
CC
V
EE
(+11.4 to +16.5V
DC
)
All Bits = 2V, Unipolar
(-11.4 to -16.5V
DC
)
All Bits = 2V, Unipolar
-
-
3
15
10
25
-
-
3
15
10
25
ppm of
FS/%
ppm of
FS/%
-
-
9.0
-9.5
11.8
-14.5
-
-
9.0
-9.5
11.8
-14.5
mA
mA
(Note 2)
(Note 2)
-
-
15
30
30
50
-
-
15
30
30
50
ns
ns
PROGRAMMABLE OUTPUT RANGES
(See Table 2)
Unipolar 5
Bipolar 5
Unipolar 10
Bipolar 10
Bipolar 20
EXTERNAL ADJUSTMENTS
Gain Error
Bipolar Zero Error
Gain Adjustment Range
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage, Commercial Versions
Voltage, /883 Versions
Current (Available for External Loads)
NOTES:
2. Guaranteed by characterization or design but not tested over the operating temperature range.
3. See settling time discussion and Figure 3.
4. The Power Supply Gain Sensitivity is tested in reference to a V
CC
, V
EE
of
±
15V.
9.90
9.95
1.5
10.00
10.00
2.5
10.10
10.05
-
9.90
9.95
1.5
10.00
10.00
2.5
10.10
10.05
-
V
V
mA
(Note 2)
15K
20K
25K
15K
20K
25K
Ω
R2 = 50Ω (Figure 2)
R3 = 50Ω (Figure 3)
(Figure 1) (Note 2)
(Note 2)
-
-
±0.25
±0.15
±0.1
±0.05
-
-
±0.25
±0.15
-
-
-
-
±0.25
±0.15
±0.1
±0.05
-
-
±0.25
±0.1
-
-
% of FS
% of FS
% of FS
% of FS
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
0 to +5
-2.5 to +2.5
0 to +10
-5 to +5
-10 to +10
0 to +5
-2.5 to +2.5
0 to +10
-5 to +5
-10 to +10
V
V
V
V
V
3
HI-565A
Definitions of Specifications
Digital Inputs
The HI-565A accepts digital input codes in binary format and
may be user connected for any one of three binary codes.
Straight Binary, Two’s Complement (Note 5), or Offset
Binary, (See Operating Instructions).
TABLE 1.
ANALOG OUTPUT
DIGITAL
INPUT
MSB...LSB
000...000
100...000
111...111
011...111
NOTE:
5. Invert MSB with external inverter to obtain Two’s Complement
Coding.
Zero
1
/ FS
2
Power Supply Sensitivity
is a measure of the change in
gain and offset of the D/A converter resulting from a change
in -15V or +15V supplies. It is specified under DC conditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
Compliance Voltage
is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only, and
makes no claims to accuracy.
Glitch
a glitch on the output of a D/A converter is a transient
spike resulting from unequal internal ON-OFF switching
times. Worst case glitches usually occur at half-scale or the
major carry code transition from 011...1 to 100...0 or vice
versa. For example, if turn ON is greater than turn OFF for
011...1 to 100...0, an intermediate state of 000...0 exists,
such that, the output momentarily glitches toward zero
output. Matched switching times and fast switching will
reduce glitches considerably.
STRAIGHT
BINARY
OFFSET
BINARY
(NOTE 5)
TWO'S
COMPLEMENT
-FS
(Full Scale)
Zero
+FS - 1 LSB
Zero - 1 LSB
Zero
-FS
Zero - 1 LSB
+FS - 1 LSB
+FS - 1 LSB
1/2FS - 1 LSB
Detailed Description
Op Amp Selection
The Hl-565As current output may be converted to voltage
using the standard connections shown in Figures 1 and 2.
The choice of operational amplifier should be reviewed for
each application, since a significant trade-off may be made
between speed and accuracy.
For highest precision, use an HA-5135. This amplifier
contributes negligible error, but requires about 11µs to settle
within
±0.1%
following a 10V step.
The Intersil HA-2600/05 is the best all-around choice for this
application, and it settles in 1.5µs (also to
±0.1%
following a
10V step). Remember, settling time for the DAC amplifier
combination is the square root of t
D2
plus t
A2
, where t
D
, t
A
are settling times for the DAC and amplifier.
Nonlinearity
of a D/A converter is an important measure of
its accuracy. It describes the deviation from an ideal straight
line transfer curve drawn between zero (all bits OFF) and full
scale (all bits ON) (End Point Method).
Differential Nonlinearity
for a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of
±1
LSB or less guarantees
monotonicity; i.e., the output always increases for an
increasing input.
Settling Time
is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within
±0.5
LSB of final value.
Gain Drift
is the change in full scale analog output over the
specified temperature range, expressed in parts per million
of full scale range per
o
C (ppm of FSR/
o
C). Gain error is
measured with respect to 25
o
C at high (T
H
) and low (T
L
)
temperatures. Gain drift is calculated for both high (T
H
-25
o
C) and low ranges (25
o
C -T
L
) by dividing the gain error
by the respective change in temperature. The specification is
the larger of the two representing worst-case drift.
Offset Drift
is the change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per
o
C (ppm of FSR/
o
C). Offset error
is measured with respect to 25
o
C at high (T
H
) and low (T
L
)
temperatures. Offset Drift is calculated for both high (T
H
-25
o
C) and low (25
o
C -T
L
) ranges by dividing the offset error
by the respective change in temperature. The specification
given is the larger of the two, representing worst-case drift.
4
No-Trim Operation
The Hl-565A will perform as specified without calibration
adjustments. To operate without calibration, substitute 50Ω
resistors for the 100Ω trimming potentiometers: In Figure 1
replace R2 with 50Ω also remove the network on pin 8 and
connect 50Ω to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50Ω resistors.
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical unipolar
zero will be
±0.5
LSB plus the op amp offset.
The feedback capacitor, C, must be selected to minimize
settling time.
Calibration
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero. For
the Hl-565A, these adjustments are similar whether the
current output is used, or whether an external op amp is
HI-565A
added to convert this current to a voltage. Refer to Table 2
for the voltage output case, along with Figure 1 or Figure 2.
Calibration is a two step process for each of the five output
ranges shown in Table 2. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e., affects each code by
the same amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum value is the same as for integral
nonlinearity error. In general, only two values of output may
be calibrated exactly; all others must tolerate some error.
Choosing the extreme end points (plus and minus full scale)
minimizes this distributed error for all other codes.
射频识别(Radio Frequency Identification，RFID)技术是一种利用无线射频通信实现的非接触式自动识别技术，与目前广泛采用的条形码技术相比，RFID具有容量大、识别距离远、穿透能力强、抗污性强等特点。RFID技术已经发展得比较成熟并获得了大规模商用，但超高频RFID技术相对滞后。本文分析了射频芯片nRF9E5的功能特性，并将其用于RFID系统中，设计了一套有源超高频(...[详细]
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